HD6433024F 查看數據表（PDF） - Hitachi -> Renesas Electronics

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HD6433024F

Hitachi Single-Chip Microcomputer

Hitachi -> Renesas Electronics 

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Contention between 16TCNT Write and Overflow ............................................. 258

Contention between General Register Read and Input Capture........................... 259

Contention between Counter Clearing by Input Capture and Counter Increment 260

Contention between General Register Write and Input Capture.......................... 261

Block Diagram of 8-Bit Timer Unit (Two Channels: Group 0)........................... 269

8TCNT Access Operation (CPU Writes to 8TCNT, Word) ................................ 283

8TCNT Access Operation (CPU Reads 8TCNT, Word)...................................... 283

8TCNT0 Access Operation (CPU Writes to 8TCNT0, Upper Byte) ................... 283

8TCNT1 Access Operation (CPU Writes to 8TCNT1, Lower Byte) .................. 284

8TCNT0 Access Operation (CPU Reads 8TCNT0, Upper Byte) ........................ 284

8TCNT1 Access Operation (CPU Reads 8TCNT1, Lower Byte)........................ 284

Count Timing for Internal Clock Input ................................................................ 285

Count Timing for External Clock Input (Both-Edge Detection).......................... 286

Timing of Timer Output ....................................................................................... 286

Timing of Clear by Compare Match .................................................................... 287

Timing of Clear by Input Capture ........................................................................ 287

Timing of Input Capture Input Signal .................................................................. 288

CMF Flag Setting Timing when Compare Match Occurs.................................... 288

CMFB Flag Setting Timing when Input Capture Occurs .................................... 289

Timing of OVF Setting ........................................................................................ 289

Example of Pulse Output...................................................................................... 294

Contention between 8TCNT Write and Clear...................................................... 295

Contention between 8TCNT Write and Increment .............................................. 296

Contention between TCOR Write and Compare Match ...................................... 297

Contention between TCOR Read and Input Capture ........................................... 298

Contention between Counter Clearing by Input Capture and Counter Increment 299

Contention between TCOR Write and Input Capture .......................................... 300

Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode . 301

TPC Block Diagram ............................................................................................. 306

TPC Output Operation.......................................................................................... 321

Timing of Transfer of Next Data Register Contents and Output (Example)........ 322

Setup Procedure for Normal TPC Output (Example) .......................................... 323

Normal TPC Output Example (Five-Phase Pulse Output) ................................... 324

Setup Procedure for Non-Overlapping TPC Output (Example) .......................... 325

Non-Overlapping TPC Output Example

(Four-Phase Complementary Non-Overlapping Pulse Output) ........................... 326

TPC Output Triggering by Input Capture (Example) .......................................... 327

Non-Overlapping TPC Output ............................................................................. 328

Non-Overlapping Operation and NDR Write Timing.......................................... 329

WDT Block Diagram ........................................................................................... 332

Format of Data Written to TCNT and TCSR ....................................................... 337

Format of Data Written to RSTCSR .................................................................... 338

Operation in Watchdog Timer Mode ................................................................... 339

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