HD6433024F 查看數據表（PDF） - Hitachi -> Renesas Electronics

零件编号

产品描述 (功能)

生产厂家

HD6433024F

Hitachi Single-Chip Microcomputer

Hitachi -> Renesas Electronics 

Figure 18.2

Figure 18.3

Figure 18.4

Figure 18.5

Figure 18.6

Figure 18.7

Figure 18.8

Figure 18.9

Figure 18.10

Figure 18.11

Figure 18.12

Figure 18.13

Figure 18.14

Figure 18.15

Figure 18.16

Figure 18.17

Figure 18.18

Figure 19.1

Figure 19.2

Figure 19.3

Figure 19.4

Figure 19.5

Figure 19.6

Figure 19.7

Figure 20.1

Figure 20.2

Figure 20.3

Figure 21.1

Figure 21.2

Figure 21.3

Figure 21.4

Figure 21.5

Figure 21.6

Figure 21.7

Figure 21.8

Figure 21.9

Figure 21.10

Figure 21.11

Figure 21.12

Figure 21.13

Figure 21.14

xx

Example of ROM Area/RAM Area Overlap........................................................ 523

Flash Memory Related State Transitions ............................................................. 525

Reading Overlap RAM Data in User Mode/User Program Mode ....................... 528

Writing Overlap RAM Data in User Program Mode ........................................... 529

System Configuration When Using Boot Mode .................................................. 531

Boot Mode Execution Procedure.......................................................................... 532

RAM Areas in Boot Mode ................................................................................... 534

Example of User Program Mode Execution Procedure ....................................... 537

FLMCR1 Bit Settings and State Transitions........................................................ 539

Program/Program-Verify Flowchart (128-Byte Programming)........................... 544

Erase/Erase-Verify Flowchart (Single-Block Erasing) ........................................ 546

Flash Memory State Transitions (When High Level is Applied to FWE Pin

in Mode 5 or 7 (On-Chip ROM Enabled)) ........................................................... 550

Example of RAM Overlap Operation .................................................................. 551

Memory Map in PROM Mode ............................................................................. 554

Power-On/Off Timing (Boot Mode) .................................................................... 558

Power-On/Off Timing (User Program Mode)...................................................... 559

Mode Transition Timing

(Example: Boot Mode → User Mode ↔ User Program Mode) .......................... 560

Block Diagram of Clock Pulse Generator............................................................ 563

Connection of Crystal Resonator (Example)........................................................ 564

Crystal Resonator Equivalent Circuit................................................................... 565

Oscillator Circuit Block Board Design Precautions............................................. 565

External Clock Input (Examples) ......................................................................... 566

External Clock Input Timing................................................................................ 568

External Clock Output Settling Delay Timing ..................................................... 568

NMI Timing for Software Standby Mode (Example) .......................................... 581

Hardware Standby Mode Timing ......................................................................... 582

Starting and Stopping of System Clock Output ................................................... 584

Darlington Pair Drive Circuit (Example) ............................................................. 589

Sample LED Circuit ............................................................................................. 590

Output Load Circuit.............................................................................................. 594

Darlington Pair Drive Circuit (Example) ............................................................. 601

Sample LED Circuit ............................................................................................. 602

Output Load Circuit.............................................................................................. 606

Oscillator Settling Timing.................................................................................... 611

Reset Input Timing ............................................................................................... 612

Reset Output Timing* .......................................................................................... 612

Interrupt Input Timing.......................................................................................... 613

Basic Bus Cycle: Two-State Access .................................................................... 615

Basic Bus Cycle: Three-State Access .................................................................. 616

Basic Bus Cycle: Three-State Access with One Wait State ................................. 617

Bus-Release Mode Timing ................................................................................... 617

Share Link: