MC12430FA 查看數據表（PDF） - Motorola => Freescale

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MC12430FA

High Frequency Clock Generator

Motorola => Freescale 

MC12430

XTAL_SEL

3

FREF_EXT

2

4

16MHz

5

OE

6

S_LOAD

28

P_LOAD

7

S_DATA

27

S_CLOCK

26

MC12430 BLOCK DIAGRAM

+3.3 or 5.0V

DIV 8

2MHz

FREF

XTAL1

OSC

XTAL2

PHASE

DETECTOR

VCO

9–BIT DIV M

COUNTER

400–800

MHz

LATCH

PLL_VCC

DIV N

(1, 2, 4, 8)

LATCH

VCC0

+3.3 or 5.0V

25

24

FOUT

23

FOUT

20

TEST

0

1

9–BIT SR

0

1

2–BIT SR

LATCH

3–BIT SR

VCC1

21

+3.3 or 5.0V

8:16

9

M[8:0]

17, 18

2

N[1:0]

22, 19

PROGRAMMING INTERFACE

Programming the device amounts to properly configuring

the internal dividers to produce the desired frequency at the

outputs. The output frequency can by represented by this

formula:

FOUT = (FXTAL ÷ 8) x M ÷ N

(1)

Where FXTAL is the crystal frequency, M is the loop divider

modulus, and N is the output divider modulus. Note that it is

possible to select values of M such that the PLL is unable to

achieve loop lock. To avoid this, always make sure that M is

selected to be 200 ≤ M ≤ 400 for any input reference.

Assuming that a 16MHz reference frequency is used the

above equation reduces to:

FOUT = 2 x M ÷ N

Substituting the four values for N (1, 2, 4, 8) yields:

FOUT = 2M, FOUT = M,

FOUT = M ÷ 2 and FOUT = M ÷ 4

for 200 < M < 400

The user can identify the proper M and N values for the

desired frequency from the above equations. The four output

frequency ranges established by N are 400–800MHz,

200–400MHz, 100–200MHz and 50–100MHz respectively.

From these ranges the user will establish the value of N

required, then the value of M can be calculated based on the

appropriate equation above. For example if an output

frequency of 131MHz was desired the following steps would

be taken to identify the appropriate M and N values. 131MHz

falls within the frequency range set by an N value of 4 so N

[1:0] = 01. For N = 4 FOUT = M ÷ 2 and M = 2 x FOUT.

Therefore M = 131 x 2 = 262, so M[8:0] = 100000110.

Following this same procedure a user can generate any

whole frequency desired between 50 and 800MHz. Note that

for N > 2 fractional values of FOUT can be realized. The size

of the programmable frequency steps (and thus the indicator

of the fractional output frequencies acheivable) will be equal

to FXTAL ÷ 8 ÷ N.

For input reference frequencies other than 16MHz the set

of appropriate equations can be deduced from equation 1.

For computer applications another useful frequency base

would be 16.666MHz. From this reference one can generate

a family of output frequencies at multiples of the 33.333MHz

PCI clock. As an example to generate a 133.333MHz clock

TIMING SOLUTIONS

3

BR1333 — Rev 6

MOTOROLA

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