NT5DS16M8AW-66 查看數據表（PDF） - Nanya Technology

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NT5DS16M8AW-66

128Mb DDR333/300 SDRAM

Nanya Technology 

NT5DS32M4AT NT5DS32M4AW

NT5DS16M8AT NT5DS16M8AW

128Mb DDR333/300 SDRAM

charge to be issued to a bank that has been activated (opened) but has not yet satisfied the tRAS(min) specification. The tRAS

Truth Table 2: Clock Enable (CKE)

1. CKE n is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.

2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.

3. Command n is the command registered at clock edge n, and action n is a result of command n.

4. All states and sequences not shown are illegal or reserved.

Current State

Self Refresh

Self Refresh

Power Down

Power Down

All Banks Idle

All Banks Idle

Bank(s) Active

CKE n-1

Previous

Cycle

L

L

L

L

H

H

H

H

CKEn

Current

Cycle

Command n

Action n

L

X

Maintain Self-Refresh

H

Deselect or NOP

Exit Self-Refresh

L

X

Maintain Power-Down

H

Deselect or NOP

Exit Power-Down

L

Deselect or NOP

Precharge Power-Down Entry

L

Auto Refresh

Self Refresh Entry

L

Deselect or NOP

Active Power-Down Entry

See “Truth Table 3: Current State

H

Bank n - Command to Bank n (Same

Bank)” on page 13

Notes

1

1. Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A minimum of

200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.

Preliminary

08/01

12

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

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