VSC6511 查看數據表（PDF） - Vitesse Semiconductor

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VSC6511

Deserializer/Reclocker SMPTE 292M Serializer, Deserialzer, and

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

SMPTE 292M Serializer, Deserializer, and

Deserializer/Reclocker

Advance Product Information

VSC6511

RCLK

Figure 12: RCLK Timing Waveforms*

tL

tH

tR

VIH(MIN)

VIL(MAX)

Table 5: RCLK Performance-Deserializer and Deserializer/Reclocker Mode

Symbol

Parameter

Min Typ Max

FOFFSET

RCLK Frequency offset from

REFCLK

-1.0

+1.0

DC

RCLK duty cycle - 40% / 60% -5

+5

tH

RCLK high times

3

tL

RCLK low times

5.9

tR

RCLK rise/fall time

1.5

NOTE: The RCLK output from the CRU is 40% high and 60% low by design.

Unit

Condition

Maximum deviation when the CRU is

% not locked. Deserializer Mode. Not

100% tested.

Measured at 1.5V. Deserializer Mode

% and Deserializer/Reclocker Mode. Not

100% tested.

ns.

Measured at 1.5V. Deserializer Mode

and Deserializer/Reclocker Mode.

ns.

Measured at 1.5V. Deserializer Mode

and Deserializer/Reclocker Mode.

ns. Between VIL(MAX) and VIH(MIN)

Table 6: RCLK Performance-Serializer Mode

Symbol

Parameter

Min Typ Max Unit

Condition

DC

RCLK duty cycle

45

tH, tL

RCLK high/low times

3.5

tR

RCLK rise/fall time

55

%

Measured at 1.5V. Serializer Mode

(REFCLK=50/50). Not 100% tested.

ns.

Measured at 1.5V. Serializer Mode.

Not 100% tested.

1.5

ns.

Between VIL(MAX) and VIH(MIN). Not

100% tested

NOTE: The RCLK output is a buffered version of the REFCLK input. The above specifications assume a 50% duty cycle on the

REFCLK input.

Page 14

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Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

G52311-0, Rev 2.1

6/25/01

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