VSC6511 查看數據表（PDF） - Vitesse Semiconductor
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VSC6511 Datasheet PDF : 22 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC6511
SMPTE 292M Serializer, Deserialzer, and
Deserializer/Reclocker
Table 7: Pin Identifications
Pin #
2,3,4,6
7,8,9,11
12,13,47,46
45,43,42,41
40,38,37,36
50
64
24
Name
D0-D3
D4-D7
D8-D11
D12-D15
D16-D19
MODE0
MODE1
SCREN
30
CRC
26
FRAME
34
LINE
27
HANC
25
21,22
56,54
60,58
52,62
53,61
29
1.001
SDI, SDI
SDO0, SDO0
SDO1, SDO1
ISET0, ISET1
OE0, OE1
REFCLK
31
33
16,17
49,19
1
20,23,28,
51, 57
5,10,39,44
63
18
RCLK
LOCK
CAP0, CAP1
TEST1, TEST2
V53
VDDD
VDDP
VDDT
VREF
VDDA
Description
INPUT/OUTPUT - TTL: Bidirectional data bus. In Serializer mode, this is a 20-bit
input bus timed to REFCLK. In Deserializer mode, this is a 20-bit output bus timed
to RCLK. In Reclocker and Cable Driver mode, several of these bits are defined as
status outputs.
INPUT - TTL: Mode select inputs. See Table 2 on page 9.
INPUT - TTL: When HIGH, enables scrambling in Serializer/Deserializer modes
BIDIRECTIONAL - TTL: In Serializer Mode, CRC Generation is enabled when this
input is HIGH and disabled when LOW. In Deserializer Mode and Deserializer/
Reclocker Mode, this is an output which indicates a CRC error has occurred.
OUTPUT - TTL: In Deserializer and Deserializer/Reclocker modes, this is an output
which, when HIGH, indicates that a FRAME synchronization event is on D[0:19].
OUTPUT - TTL: In Deserializer and Deserializer/Reclocker modes, this is an output
which, when HIGH, indicates that a LINE synchronization event is on D[0:19].
OUTPUT- TTL: Output which is HIGH during the Horizontal Blanking period
between EAV and SAV.
OUTPUT - TTL: When HIGH, indicates that a valid receive signal is present on SDI/
SDI and that the SMPTE-292M incoming data is greater than 500ppm from
20xREFCLK. NOTE: This output is not tested.
INPUT - Differential. Serial input to CRU.
OUTPUT - Differential. High-Speed Cable Driver output.
Serial output from the Serializer, Reclocker or SDI/SDI input buffer.
Connect resistor to ground to set the output swing of SDO0, and SDO1
INPUT - TTL. Output enable pins for SDO0, and SDO1. Enabled when HIGH for
each output.
INPUT - TTL. Reference Clock at 74.25MHz or 74.25/1.001MHz. This is the input
to the CMU used to generate the20X serializing clock in Serializer Mode.
OUTPUT - TTL: Output clock. In Serializer and Reclocker Mode, this is a buffered
version of REFCLK. In Deserializer Mode, this is the recovered clock used to time
D[19:0].
OUTPUT - TTL. Output signal that indicates when the PLL is in lock.
Analog I/O: Loop Filter Capacitor, 0.1µF nominal, 3V swing maximum
INPUT - TTL. LOW for factory test, HIGH for normal operation.
INPUT - POWER: This power supply would normally be 3.3V. If 5V tolerance for
D[19:0] is required, this pin should be connected to 5V supply.
Power Supply. 3.3V Supply for digital logic.
Power Supply. 3.3V Supply for Cable Driver output stage. Keep isolated from digital
power and grounds.
TTL I/O Power Supply.
Voltage Reference Input. If used, this is biased to 1.25V.
Analog Power Supply. 3.3V for Clock Multiplier PLL. Bypass to pin 15.
G52311-0, Rev 2.1
6/25/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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