EP1C12 查看數據表（PDF） - Unspecified

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EP1C12

Cyclone FPGA Family

Unspecified 

Cyclone FPGA Family Data Sheet

Preliminary Information

Normal Mode

The normal mode is suitable for general logic applications and

combinatorial functions. In normal mode, four data inputs from the LAB

local interconnect are inputs to a four-input LUT (see Figure 6). The

Quartus II Compiler automatically selects the carry-in or the data3 signal

as one of the inputs to the LUT. Each LE can use LUT chain connections to

drive its combinatorial output directly to the next LE in the LAB.

Asynchronous load data for the register comes from the data3 input of

the LE. LEs in normal mode support packed registers.

Figure 6. LE in Normal Mode

sload

sclear

(LAB Wide) (LAB Wide)

Register chain

connection

aload

(LAB Wide)

addnsub (LAB Wide)

(1)

data1

data2

data3

cin (from cout

of previous LE)

data4

4-Input

LUT

clock (LAB Wide)

ena (LAB Wide)

aclr (LAB Wide)

ALD/PRE

ADATA Q

D

ENA

CLRN

Row, column, and

direct link routing

Row, column, and

direct link routing

Local routing

LUT chain

connection

Register Feedback

Register

chain output

Note to Figure 6:

(1) This signal is only allowed in normal mode if the LE is at the end of an adder/subtractor chain.

12

Altera Corporation

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