EP1C12 查看數據表（PDF） - Unspecified

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产品描述 (功能)

生产厂家

EP1C12

Cyclone FPGA Family

Unspecified 

Cyclone FPGA Family Data Sheet

Figure 8. Carry Select Chain

LAB Carry-In

A1

B1

A2

B2

A3

B3

A4

B4

A5

B5

01

LE1

Sum1

LE2

Sum2

LE3

Sum3

LE4

Sum4

LE5

Sum5

01

A6

LE6

Sum6

B6

A7

LE7

Sum7

B7

A8

LE8

Sum8

B8

A9

LE9

Sum9

B9

A10

LE10 Sum10

B10

Preliminary Information

LAB Carry-In

Carry-In0

Carry-In1

data1

data2

LUT

Sum

LUT

LUT

LUT

Carry-Out0 Carry-Out1

LAB Carry-Out

The Quartus II Compiler automatically creates carry chain logic during

design processing, or the designer can create it manually during design

entry. Parameterized functions such as LPM functions automatically take

advantage of carry chains for the appropriate functions.

The Quartus II Compiler creates carry chains longer than 10 LEs by

linking LABs together automatically. For enhanced fitting, a long carry

chain runs vertically allowing fast horizontal connections to M4K

memory blocks. A carry chain can continue as far as a full column.

16

Altera Corporation

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