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EP1C12

Cyclone FPGA Family

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Cyclone FPGA Family Data Sheet

Preliminary Information

The R4 interconnects span four LABs, or two LABs and one M4K RAM

block. These resources are used for fast row connections in a four-LAB

region. Every LAB has its own set of R4 interconnects to drive either left

or right. Figure 9 shows R4 interconnect connections from an LAB. R4

interconnects can drive and be driven by M4K memory blocks, PLLs, and

row IOEs. For LAB interfacing, a primary LAB or LAB neighbor can drive

a given R4 interconnect. For R4 interconnects that drive to the right, the

primary LAB and right neighbor can drive on to the interconnect. For R4

interconnects that drive to the left, the primary LAB and its left neighbor

can drive on to the interconnect. R4 interconnects can drive other R4

interconnects to extend the range of LABs they can drive. R4 interconnects

can also drive C4 interconnects for connections from one row to another.

Figure 9. R4 Interconnect Connections

Adjacent LAB can

Drive onto Another

LAB's R4 Interconnect

R4 Interconnect

Driving Left

C4 Column Interconnects (1)

R4 Interconnect

Driving Right

LAB

Neighbor

Primary

LAB (2)

Notes to Figure 9:

(1) C4 interconnects can drive R4 interconnects.

(2) This pattern is repeated for every LAB in the LAB row.

LAB

Neighbor

The column interconnect operates similarly to the row interconnect. Each

column of LABs is served by a dedicated column interconnect, which

vertically routes signals to and from LABs, M4K memory blocks, and row

and column IOEs. These column resources include:

■ LUT chain interconnects within an LAB

■ Register chain interconnects within an LAB

■ C4 interconnects traversing a distance of four blocks in an up and

down direction

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Altera Corporation

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