EP1C12 查看數據表（PDF） - Unspecified

零件编号

产品描述 (功能)

生产厂家

EP1C12

Cyclone FPGA Family

Unspecified 

Cyclone FPGA Family Data Sheet

Preliminary Information

Figure 7. LE in Dynamic Arithmetic Mode

LAB Carry-In

Carry-In0

Carry-In1

addnsub

(LAB Wide)

(1)

sload

sclear

(LAB Wide) (LAB Wide)

Register chain

connection

aload

(LAB Wide)

data1

data2

data3

LUT

ALD/PRE

ADATA Q

D

LUT

ENA

CLRN

clock (LAB Wide)

LUT

ena (LAB Wide)

aclr (LAB Wide)

LUT

Register Feedback

Carry-Out0 Carry-Out1

Note to Figure 7:

(1) The addnsub signal is tied to the carry input for the first LE of a carry chain only.

Row, column, and

direct link routing

Row, column, and

direct link routing

Local routing

LUT chain

connection

Register

chain output

Carry-Select Chain

The carry-select chain provides a very fast carry-select function between

LEs in dynamic arithmetic mode. The carry-select chain uses the

redundant carry calculation to increase the speed of carry functions. The

LE is configured to calculate outputs for a possible carry-in of 0 and carry-

in of 1 in parallel. The carry-in0 and carry-in1 signals from a lower-

order bit feed forward into the higher-order bit via the parallel carry chain

and feed into both the LUT and the next portion of the carry chain. Carry-

select chains can begin in any LE within an LAB.

The speed advantage of the carry-select chain is in the parallel pre-

computation of carry chains. Since the LAB carry-in selects the

precomputed carry chain, not every LE is in the critical path. Only the

propagation delays between LAB carry-in generation (LE 5 and LE 10) are

now part of the critical path. This feature allows the Cyclone architecture

to implement high-speed counters, adders, multipliers, parity functions,

and comparators of arbitrary width.

14

Altera Corporation

Share Link: