CS53L32A 查看數據表（PDF） - Cirrus Logic

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CS53L32A

Low Voltage, Stereo A/D Converter

Cirrus Logic 

CS53L32A

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE

(TA = 25 °C; VL = 1.7V - 3.6V; Inputs: logic 0 = GND, logic 1 = VL, CL = 30 pF)

Parameter

SPI Mode

CCLK Clock Frequency

RST Rising Edge to CS Falling

CCLK Edge to CS Falling

CS High Time Between Transmissions

CS Falling to CCLK Edge

CCLK Low Time

CCLK High Time

CDIN to CCLK Rising Setup Time

CCLK Rising to DATA Hold Time

Rise Time of CCLK and CDIN

Fall Time of CCLK and CDIN

Symbol

Min

fsclk

-

tsrs

500

(Note 9)

tspi

500

tcsh

1.0

tcss

20

tscl

66

tsch

66

tdsu

40

(Note 10)

tdh

15

(Note 11)

tr2

-

(Note 11)

tf2

-

Max

6

-

-

-

-

-

-

-

-

100

100

Unit

MHz

ns

ns

µs

ns

ns

ns

ns

ns

ns

ns

Notes: 9. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.

10. Data must be held for sufficient time to bridge the transition time of CCLK.

11. For FSCLK < 1 MHz.

RST

t srs

CS

t spi t css

t scl t sch

t csh

CCLK

t r2

t f2

CDIN

t dsu t dh

Figure 4. Control Port Timing - SPI Mode

12

DS513PP1

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