CS53L32A 查看數據表（PDF） - Cirrus Logic

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CS53L32A

Low Voltage, Stereo A/D Converter

Cirrus Logic 

CS53L32A

3. REGISTER QUICK REFERENCE

** “default” ==> bit status after power-up-sequence or reset.

3.1 I/O and Power Control (address 01h)

7

RESERVED

0

6

BOOST

0

5

AINMUX1

0

4

AINMUX0

0

3

RESERVED

0

2

RESERVED

0

1

PDN

1

BOOST

20 dB Digital Gain

Default = ‘0’

0 - Disabled

1 - Enabled

AINMUX

Analog Input Mulitplexer

Default =’0’.

0 - AIN_L1/AIN_R1 direct to A/D (default)

1 - AIN_L2/AIN_R2 direct to A/D

2 - AIN_L2/AIN_R2 through PGA to A/D

3 - Reserved

PDN

Power-Down

Default =’1’.

0 - Disabled

1 - Enabled

CP_EN

Control Port Enable

Default =’0’.

0 - Disabled

1 - Enabled

3.2 Interface Control (address 02h)

7

RESERVED

0

6

MCLKDIV

0

5

RATIO1

0

4

RATIO0

0

3

MASTER

0

2

DIF2

0

1

DIF1

0

MCLKDIV

RATIO1-0

MASTER

Master Clock Divider

Default =’0’.

0 - Disabled

1 - Enabled

Master Clock Ratio

Default =’0’.

0 - 128x (default)

1 - 192x

2 - 256x

3 - 384x

Master Mode

Default =’0’.

0 - Slave Mode

1 - Master Mode

0

CP_EN

0

0

DIF0

0

14

DS513PP1

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