CS53L32A 查看數據表（PDF） - Cirrus Logic

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CS53L32A

Low Voltage, Stereo A/D Converter

Cirrus Logic 

CS53L32A

DIF2-0

Digital Interface Format

Default = ‘0’.

0 - I2S, up to 24-bit Data, Data valid on positive edge of SLCK (default)

1 - Left Justified, up to 24-bit Data, Data valid on positive edge of SLCK

2 - Reserved

3 - Right Justified, 16-bit Data, Data valid on positive edge of SLCK

4 - Right Justified, 24-bit Data, Data valid on positive edge of SLCK

5 - Right Justified, 18-bit Data, Data valid on positive edge of SLCK

6 - Right Justified, 20-bit Data, Data valid on positive edge of SLCK

7 - Reserved

3.3 Analog I/O Control (address 03h)

7

MUTEL

0

6

MUTER

0

5

SOFT

1

4

3

2

ZC

RESERVED

INDVC

1

0

0

1

0

L=R

HPFREEZE

0

0

MUTEL

MUTER

SOFT

ZC

INDVC

L=R

HPFREEZE

Left Channel Mute

Default = ‘0’.

0 - Disabled

1 - Enabled

Right Channel Mute

Default = ‘0’.

0 - Disabled

1 - Enabled

Soft Digital/Analog Volume Control

Default = ‘1’.

0 - Disabled

1 - Enabled

Analog Zero Cross Detection Control

Default = ‘1’.

0 - Disabled

1 - Enabled

Independent Volume Control Enable

Default = ‘0’.

0 - Disabled

1 - Enabled

Left Channel Volume = Right Channel Volume

Default = ‘0’.

0 - Left channel volume is determined by the left channel volume control registers and right

channel volume is determined by the right channel volume control registers.

1 - Left and right channel volumes are determined by the left channel volume control registers

and the right channel volume control registers are ignored.

High-pass filter freeze

Default = ‘0’.

0 - Disabled

1 - Enabled

DS513PP1

15

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