CS53L32A 查看數據表（PDF） - Cirrus Logic

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CS53L32A

Low Voltage, Stereo A/D Converter

Cirrus Logic 

CS53L32A

4.5 MASTER CLOCK DIVIDE

Interface Control Register (address 02h)

7

RESERVED

6

MCLKDIV

5

RATIO1

4

RATIO0

3

MASTER

2

DIF2

Access:

R/W in Two Wire Mode and write only in SPI.

1

DIF1

0

DIF0

Default:

0 - Disabled

Function:

Divides MCLK by two prior to all other chip circuitry.

MCLKDIV

0

1

MODE

Disabled

Enabled

Table 4. Master Clock Divide Select

4.6 MASTER CLOCK RATIO

Interface Control Register (address 02h)

7

RESERVED

6

MCLKDIV

5

RATIO1

4

RATIO0

3

MASTER

Access:

R/W in Two Wire Mode and write only in SPI.

2

DIF2

1

DIF1

0

DIF0

Default:

0 - 128x

Function:

Sets the ratio of MCLK to LRCK.

RATIO1,0

0

1

2

3

MCLK/LRCK RATIO (MCLKDIV=0)

128x

192x

256x

384x

MCLK/LRCK RATIO (MCLKDIV=1)

256x

384x

512x

768x

Table 5. MCLK/LRCK Ratios

DS513PP1

19

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