VSC7216UC-01 查看數據表（PDF） - Vitesse Semiconductor

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VSC7216UC-01

Multi-Gigabit Interconnect Chip

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Multi-Gigabit Interconnect Chip

Multi-Gigabit Interconnect Chip

Preliminary Data Sheet

VSCV7S2C1672-0116

‘EFGH’, ‘IJKL’, etc., the receiver should not recover data words as ‘ABGD’, ‘EFKH’, ‘IJOL’, etc. This requires

the four transmit channels to obtain input data on a common clock (e.g., TMODE(2:0)=000 or 1X0) and the

four receive channels to present output data on a common word clock (e.g., RMODE(1:0)=0X or 10).

Within the receiver there are elastic buffers used to deskew the four channels and align them to a common

word clock. An elastic buffer allows the channels’ input to be skewed up to ±6 bit times (12 bit times total skew

between any two channels) in order to accommodate circuit imperfections, differences in transmission delay

and jitter. Multiple VSC7216-01 devices can also be used in synchronous operation if the skew between all

serial input pairs is maintained less than ±6 serial clock bit times. This allows easy implementation of robust

systems, and is discussed in greater detail in the Using Multiple VSC7216-01s in Parallel section.

In order to perform word alignment, a synchronization point must be seen across all aligned receive

channels within the +/-6 bit time window. The VSC7216-01 receiver recognizes the first four characters of the

Word Sync Sequence (either K28.5+ K28.5+ K28.5- K28.5- or K28.5- K28.5- K28.5+ K28.5+) as the

synchronization point. As a model for understanding, consider the case where a VSC7216-01 transmitter sends

32 bits of data to the receiver via copper media which has small cable length differences causing a channel-to-

channel skew. All transmit channels that are to be word aligned transmit the Word Sync Sequence in parallel.

On detection of the synchronization point, the receivers will reposition the recovered data within their elastic

buffers in order to align all four channels and remove any channel-to-channel skew. All normal data characters

following the Word Sync Sequence will be properly word aligned. In the process of channel alignment, one or

two of the final twelve K28.5 characters in the Word Sync Sequence may be deleted or duplicated. This ensures

that each transmitted 32-bit word is recovered correctly.

The VSC7216-01 is capable of performing rate matching in word-aligned applications by inserting or

deleting IDLEs in parallel across the aligned receive channels. This requires that the word-aligned data streams

contain IDLEs inserted in parallel on all transmit channels (e.g., an IDLE “word”) according to the IDLE

density requirement previously described.

Word alignment is enabled by connecting the WSI input to a WSO output, either from the same device if a

single device is used, or from another device if multiple devices are used in parallel to align more than four

channels. The FLOCK input state and WSI input source determine whether or not rate matching (IDLE deletion

or duplication) will be performed, and whether it is done independently on each channel or in parallel across

aligned channels. Word alignment is disabled when WSI is not connected to a WSO output. Rate matching is

disabled when either FLOCK is HIGH or WSI is held LOW (see Table 7).

Table 7: Word Alignment and Rate Matching Control

FLOCK

0

0

0

1

1

1

WSI Source

0

1

WSO

0

1

WSO

Word Alignment

Off

Off

Enabled

Off

Off

Enabled

Rate Matching

Off

Enabled, Independent Channels

Enabled, Aligned Channels

Off

Off

Off

Page 12

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Internet: www.vitesse.com

G52352-0, Rev 3.2

05/05/01

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