VSC7216UC-01 查看數據表（PDF） - Vitesse Semiconductor

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VSC7216UC-01

Multi-Gigabit Interconnect Chip

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Multi-Gigabit Interconnect Chip

Multi-Gigabit Interconnect Chip

Preliminary Data Sheet

VSCV7S2C1672-0116

In Parallel Loopback mode the receiver uses an internal copy of REFCLK as the word clock in each

receiver. This data is looped back to the transmitter with TMODE(2:0) internally set to 000. This guarantees

that the parallel loopback data to be re-transmitted will be frequency-locked to the transmitter’s REFCLK, but

means that the receiver parallel output data timing will not match the normal system timing that is externally

selected by RMODE(1:0), so the parallel output data should be ignored in this mode of operation.

This internal loopback configuration also allows rate matching to be performed in the receivers’ elastic

buffers. Rate matching is controlled and operates exactly the same way that it does in normal mode. This is

needed to avoid receiver Overrun/Underrun errors in the loopback device if the remote transmitting device’s

REFCLK is not frequency locked to the loopback device’s REFCLK. Keep in mind that the LBENn(1:0), RXP/

Rn, PTXENn, RTXENn and BIST inputs must all be configured appropriately in order for end-to-end parallel

loopback to function correctly in a user environment. Parallel Loopback mode is internally disabled when BIST

mode is enabled.

Built-In Self Test Operation

Built-In Self Test operation is enabled when the BIST input is HIGH, which causes TMODE(2:0) to be

internally set to 000. Upon entering BIST mode, the transmitter will issue a Word Sync Sequence in order to

recenter the elasticity buffers in the receive channel. Each transmitter then repeatedly sends a simple 256-byte

incrementing data pattern (prior to 8B/10B encoding) followed by three IDLE characters (K28.5). Note that this

incrementing pattern plus three IDLEs will cause both disparities of each data character and the IDLE character

to be transmitted, and contains a sufficient IDLE density for any application requiring IDLE insertion/deletion.

It is up to the user to enable IDLE insertion/deletion if the receiver’s word clock is not frequency-locked to the

transmitter’s REFCLK.

Each receiver monitors incoming data for this pattern and indicates if any errors are detected. Correct

reception of the pattern is reported on each receiver’s TBERRn output; a LOW means the pattern is being

received correctly and a HIGH means that errors are detected. When BIST transitions from LOW to HIGH,

each TBERRn output is initialized HIGH. It will be cleared LOW whenever one or more IDLE characters

followed by all 256 data characters are sequentially received without error, and set HIGH whenever a pattern

mis-match or receiver error is encountered. Each channel functions independently, no attempt is made to word-

align the receive channels. Received data and associated status will be output as in normal operation. Please

note that Serial Loopback mode and receiver output timing mode selection via RMODE(1:0) operate

independently of BIST mode, but BIST mode disables Parallel Loopback mode.

Figure 12: BIST Mode Operation

BIST

Gen 1

Tn(7:0)

C/Dn

WSENn

ªREFCLK

8

0

01

KCHAR

0

BIST

8

DQ

PTXENn

8B/10B 10

Encode

RTXENn

LBENn(1:0)

RXP/Rn

LBTXn

PTXn+ PRXn+

PTXn- PRXn-

RTXn+ RRXn+

RTXn- RRXn-

TRANSMITTER

Clk/Data

Recovery

PSDETn

RSDETn

8

10 8B/10B 8 Elastic

Decode 3 Buffer

WORDCLK

BIST

Chk

RECEIVER

} From Tx

Clock Gen

CGERRn

1

0

BIST

Rn(7:0)

IDLEn

KCHn

ERRn

TBERRn

Page 18

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

G52352-0, Rev 3.2

05/05/01

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