VSC7216UC-01 查看數據表（PDF） - Vitesse Semiconductor

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VSC7216UC-01

Multi-Gigabit Interconnect Chip

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Multi-Gigabit Interconnect Chip

Multi-Gigabit Interconnect Chip

Preliminary Data Sheet

VSCV7S2C1672-0116

The logic used to align the four receive channels and/or insert and delete IDLE characters to compensate

for REFCLK variations between transmitting and receiving devices is disabled when ENDEC is LOW. In order

for this mode of operation to function without errors, the word clock source as selected by RMODE(1:0) must

be frequency-locked to the REFCLK of the remote transmitting device in each channel. This is guaranteed

when RMODE(1:0) = 11. For other choices of RMODE(1:0), the frequency-locked condition must be

guaranteed by system design. When DUAL is HIGH and RMODE(1:0) = 10 or 11, the character containing the

‘0011111xxx’ “Comma” pattern is aligned to RCLKn/RCLKNn in each channel so that COMDET will be

asserted on the falling edge of RCLKn (rising edge of RCLKNn). This is done by adjusting the latency through

the elastic buffer; the recovered clock is never stretched or slivered. When the “Comma” pattern changes the

framing boundary, data characters prior to the assertion of COMDET on the falling edge of RCLKn may be

corrupted.

Receiver State Machine

Each channel contains a Loss of Synchronization State Machine (LSSM) which is responsible for detecting

and handling loss of bit, channel, word and word clock synchronization in a controlled manner. There are three

states in the LSSM: LOSS_OF_SYNC, RESYNC, and SYNC_ACQUIRED as shown in the state diagram of

Figure 9. The RESYNC state is entered when a 10-bit word has been received which contains the 7-bit Comma

pattern (e.g., a K28.5 IDLE character). After entering the RESYNC state, the VSC7216-01 will stay in it until a

valid, non-Comma transmission is received, then it transitions to the SYNC_ACQUIRED state indicating a

normal operating condition. The RESYNC state is re-entered if four consecutive “Commas” are received or if a

single “Comma” is received that changes the 10B character framing boundary. The LOSS_OF_SYNC state is

entered whenever four consecutive invalid transmissions have been detected or when the occurrences of invalid

transmission outnumber those of valid transmission by four. The relative occurrences of invalid verses valid

transmissions are monitored with a simple up/down counter that increments when an invalid transmission is

detected and decrements otherwise. The LSSM transitions to the LOSS_OF_SYNC state when the counter

reaches four, and the counter is reset. A state diagram for the invalid transmission counter is shown in

Figure 10. The VSC7216-01 receiver will stay in the LOSS_OF_SYNC state until a valid “Comma” pattern is

detected. Note that the RESYNC state is entered whenever the 10B framing boundary is changed, and whenever

the Word Sync Sequence is received. When ENDEC is LOW, the ERRn, KCHn and IDLEn outputs are re-

defined and the decoder and associated LSSM logic in each channel is unused.

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© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

G52352-0, Rev 3.2

05/05/01

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