XRT91L81 查看數據表（PDF） - Exar Corporation
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XRT91L81 Datasheet PDF : 40 Pages
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XRT91L81
2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
REV. P1.0.3
TRANSMITTER SECTION
PRELIMINARY
NAME
LEVEL
TYPE
PIN
DESCRIPTION
LOCKDET_CMU
LVTTL
O
N2 CMU Lock
This pin is used to monitor the lock condition of the clock multi-
plier unit.
"Low" = CMU out of Lock
"High" = CMU Locked
OVERFLOW
LVTTL
O
M13 Transmit FIFO Overflow
This pin is used to monitor the transmit FIFO status.
"Low" = Normal Status
"High" = Overflow Condition
FIFO_RST
LVTTL
I
N13 FIFO Control Reset
Hardware Mode FIFO_RST should be held "High" for 10 cycles
of TXCLK during power-up in order to flush out the FIFO. Upon
an interrupt indication that the FIFO has an overflow condition,
this pin is used to reset or flush out the FIFO.
NOTE: To automaically reset the FIFO, see Pin
FIFO_AUTORST.
FIFO_AUTORST
LVTTL
I
N12 Automatic FIFO Reset
Hardware Mode If this pin is set "High", the OC-48 transceiver
will automatically flush the FIFO upon an overflow condition.
Upon power-up, the FIFO should be manually reset by pulling
FIFO_RST "High" for 10 cycles of TXCLK.
"Low" = Manual FIFO reset required for overflow conditions
"High" = Automatically resets FIFO upon overflow detection
RECEIVER SECTION
NAME
LEVEL
RXD0P
RXD0N
RXD1P
RXD1N
RXD2P
RXD2N
RXD3P
RXD3N
LVDS
RXCLKP
RXCLKN
LVDS
TRIRXD
LVTTL
TYPE
O
O
I
PIN
DESCRIPTION
E13 Receive Parallel Data Output
F13 622Mbps 4-bit parallel receive output data is updated simulta-
C14 neously on the rising edge of the RXCLK output. The 4-bit par-
D14 allel interface is de-multiplexed from the receive serial input
data MSB first (RXD3P/N).
C13
D13
NOTE: The XRT91L81 can output 666Mbps 4-bit parallel
receive output data for Forward Error Correction (FEC)
A14
Applications.
B14
E14 Receive Output Clock
F14 622MHz output clock reference for the 4-bit parallel receive
output data RXDP/N[3:0].
NOTE: The XRT91L81 can output a 666MHz receive output
clock for Forward Error Correction (FEC).
C12 Tri-State Receive Parallel Data Output
Hardware Mode This pin is used to control the activity of the 4-
bit parallel receive output bus and its reference clock.
"Low" = Normal Mode
"High" = Tri-State RXDP/N[3:0] and RXCLK
8
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