DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

DSP56F805 查看數據表(PDF) - Freescale Semiconductor

零件编号
产品描述 (功能)
生产厂家
DSP56F805
Freescale
Freescale Semiconductor Freescale
DSP56F805 Datasheet PDF : 56 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
2.3 Clock and Phase Locked Loop Signals
Clock and Phase Locked Loop Signals
Table 2-5 PLL and Clock
No. of
Pins
1
1
Signal
Name
EXTAL
Signal
Type
Input
XTAL Input/O
utput
State During
Reset
Input
Chip-driven
Signal Description
External Crystal Oscillator Input—This input should be
connected to an 8MHz external crystal or ceramic resonator. For
more information, please refer to Section 3.5.
Crystal Oscillator Output—This output should be connected to
an 8MHz external crystal or ceramic resonator. For more
information, please refer to Section 3.5.
This pin can also be connected to an external clock source. For
more information, please refer to Section 3.5.3.
1
CLKO Output Chip-driven Clock Output—This pin outputs a buffered clock signal. By
programming the CLKOSEL[4:0] bits in the CLKO Select
Register (CLKOSR), the user can select between outputting a
version of the signal applied to XTAL and a version of the
device’s master clock at the output of the PLL. The clock
frequency on this pin can also be disabled by programming the
CLKOSEL[4:0] bits in CLKOSR.
2.4 Address, Data, and Bus Control Signals
Table 2-6 Address Bus Signals
No. of
Pins
6
2
Signal
Name
A0–A5
A6–A7
GPIOE2
GPIOE3
Signal
Type
Output
Output
Input/O
utput
State During
Reset
Tri-stated
Tri-stated
Input
Signal Description
Address Bus—A0–A5 specify the address for external
Program or Data memory accesses.
Address Bus—A6–A7 specify the address for external
Program or Data memory accesses.
Port E GPIO—These two General Purpose I/O (GPIO) pins
can be individually programmed as input or output pins.
After reset, the default state is Address Bus.
8
A8–A15 Output
Tri-stated
Address Bus—A8–A15 specify the address for external
Program or Data memory accesses.
Input
GPIOA0Input/O
Port A GPIO—These eight General Purpose I/O (GPIO) pins
GPIOA7 utput
can be individually be programmed as input or output pins.
After reset, the default state is Address Bus.
56F805 Technical Data, Rev. 15
Freescale Semiconductor
11

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]