ADC0801S040 查看數據表（PDF） - NXP Semiconductors.
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ADC0801S040 Datasheet PDF : 19 Pages
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NXP Semiconductors
ADC0801S040
Single 8 bits ADC, up to 40 MHz
Table 6. Characteristics …continued
VDDA = V5 to V6 = 3.3 V; VDDD = V3 to V4 = 3.3 V; VDDO = V20 to V11 = 3.3 V; VSSA, VSSD and VSSO shorted together; Vi(a)(p-p)
= 1.84 V; CL = 20 pF; Tamb = 0 °C to 70 °C; typical values measured at Tamb = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Digital outputs D7 to D0 and IR (Referenced to VSSD)
VOL
LOW-level output
IO = 1 mA
voltage
0
-
0.5
V
VOH
HIGH-level output
IO = −1 mA
voltage
VDDO − 0.5 -
VDDO
V
IOZ
OFF-state output current 0.4 V < VO < VDDO
Clock input CLK; see Figure 4[1]
−20
-
+20
µA
fclk(max)
maximum clock
frequency
40
-
-
MHz
tw(clk)H
HIGH clock pulse width
tw(clk)L
LOW clock pulse width
Analog signal processing (fclk = 40 MHz)
Linearity
9
-
-
ns
9
-
-
ns
INL
integral non-linearity
ramp input; see Figure 6
-
±0.5
±0.75
LSB
DNL
differential non-linearity ramp input; see Figure 7
-
±0.25
±0.5
LSB
Bandwidth
B
bandwidth
full-scale sine wave
[4] -
10
MHz
75 % full-scale sine wave
-
13
MHz
50 % full-scale sine wave
-
20
MHz
small signal at mid scale;
-
350
Vi = ±10 LSB at code 128
Input set response; see Figure 8[5]
MHz
ts(LH)
LOW to HIGH settling full-scale square wave
-
time
3
5
ns
ts(HL)
HIGH to LOW settling full-scale square wave
-
time
3
5
ns
Harmonics; see Figure 9[6]
THD
total harmonic distortion fi = 4.43 MHz
Signal-to-Noise ratio; see Figure 9[6]
-
−50
-
dB
S/N
signal-to-noise ratio
Effective bits; see Figure 9[6]
without harmonics;
fi= 4.43 MHz
-
47
-
dB
ENOB
effective number of bits
Differential gain[7]
fi = 300 MHz
fi = 4.43 MHz
-
7.8
-
bits
-
7.3
-
bits
Gdif
differential gain
PAL modulated ramp
-
1.5
-
%
ADC0801S040_2
Product data sheet
Rev. 02 — 18 August 2008
© NXP B.V. 2008. All rights reserved.
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