MSM80C88A-10GS-K 查看數據表（PDF） - Oki Electric Industry

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MSM80C88A-10GS-K

8-Bit CMOS MICROPROCESSOR

Oki Electric Industry 

¡ Semiconductor

MSM80C88A-10RS/GS/JS

Minimum Mode (continued)

CLK (MSM82C84A-2 Output)

VIH

VIL

IO/M, SS0

A19/S6 - A16/S3

ALE

Write Cycle

(NOTE 1)

RD, INTA

DT/R = VOH

AD7 - AD0

DEN

WR

tCHCTV

tCLCL

T2

tCH1CH2

tCHCL

tCLAV

tCLLH

tCLAV

tCLAX tCLDV

A19 - A16

tLHLL

tLLAX

tAVAL

tCHLL ttCCLLDAXV

AD7 - AD0

tCVCTV

tAVAL

tLLAX

tCVCTV

AD7 - AD0

INTA Cycle

(NOTES 1 & 3)

(RD, WR = VOH

BHE = VOL)

DT/R

INTA

DEN

tCLAZ

tCHCTV

Float

tCVCTV

tCVCTV

T3 TW

T4

tCL2CL1

tCLCH

S6 - S3

tCHDX

Data Out

tCHDX

tWHDX tCVCTX

tWLWH

tCVCTX

tDVCL

Pointer

tCLDX

Float

tCHCTV

tCVCTX

Software Halt

RD, WR, INTA = VOH

DT/R = Indeterminate

tCLAV

Invalid Address

Software Halt TCLAV

Notes: 1. All signals switch between VOH and VOL unless otherwise specified.

2. RDY is sampled near the end of T2, T3, TW to determine if TW machines states are

to be inserted.

3. Two INTA cycles run back-to-back. The MSM80C88A-10 LOCAL ADDR/DATA

BUS is floating during both INTA cycles. Control signals shown for second INTA

cycle.

4. Signals at MSM82C84A-2 shown for reference only.

5. All timing measurements are made at 1.5 V unless otherwise noted.

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