PCA9555 查看數據表（PDF） - NXP Semiconductors.
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PCA9555 Datasheet PDF : 34 Pages
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NXP Semiconductors
PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
6.5.2 Reading the port registers
In order to read data from the PCA9555, the bus master must first send the PCA9555
address with the least significant bit set to a logic 0 (see Figure 8 “PCA9555 device
address”). The command byte is sent after the address and determines which register will
be accessed. After a restart, the device address is sent again, but this time the least
significant bit is set to a logic 1. Data from the register defined by the command byte will
then be sent by the PCA9555 (see Figure 12, Figure 13 and Figure 14). Data is clocked
into the register on the falling edge of the acknowledge clock pulse. After the first byte is
read, additional bytes may be read but the data will now reflect the information in the other
register in the pair. For example, if you read Input Port 1, then the next byte read would be
Input Port 0. There is no limitation on the number of data bytes received in one read
transmission but the final byte received, the bus master must not acknowledge the data.
slave address
SDA S 0 1 0 0 A2 A1 A0 0 A
COMMAND BYTE
A (cont.)
START condition
R/W
acknowledge
from slave
slave address
acknowledge
from slave
data from lower or
upper byte of register
MSB
LSB
(cont.) S 0 1 0 0 A2 A1 A0 1 A
DATA (first byte)
A
data from upper or
lower byte of register
MSB
LSB
DATA (last byte)
NA P
(repeated)
START condition
R/W
acknowledge
from slave
acknowledge
from master
no acknowledge STOP
from master condition
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
002aac222
Remark: Transfer can be stopped at any time by a STOP condition.
Fig 12. Read from register
PCA9555_8
Product data sheet
Rev. 08 — 22 October 2009
© NXP B.V. 2009. All rights reserved.
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