VSC7217 查看數據表（PDF） - Vitesse Semiconductor

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VSC7217

Multi-Gigabit Interconnect Chip

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

VSC7217

Multi-Gigabit Interconnect Chip

The elastic buffer is designed to allow a maximum phase drift of +2 or -2 serial clock bit times between re-

synchronizations, which sets a limit on the maximum data “packet” length allowed between IDLEs. This maxi-

mum packet length depends on the frequency difference between the transmitting and receiving devices REF-

CLKs. Let ∆φ represent phase drift in bit times, and let 2π represent one full 10-bit character of phase drift.

Limiting phase drift to two bit times means the following inequality must be satisfied:

(1)

∆φ ≤ (0.2 × 2π)

Let L be the number of 10-bit characters transmitted, and let ∆f be the frequency offset in ppm. The total

phase drift in bit times is given by:

(2)

∆φ = (∆f ⁄ 106) × 2πL

A simple expression for maximum packet length as a function of frequency offset is derived by substituting

Equation (2) in Equation (1) and solving for L:

(3)

L ≤ (0.2 × 106) ⁄ ∆f

As an example, if the frequency offset is 200 ppm, the maximum packet length should not be more than 1K

bytes. To increase the maximum packet length L, decrease the frequency offset ∆f. Please note that if only on

K28.5 is transmitted between “packets” of data, it might be dropped during compensation for phase drift. If the

user must have at least one K28.5 between these two packets, then two K28.5s must be transmitted.

Word Alignment

The VSC7217 performs channel-to-channel word alignment. In this mode of operation, if the data from all

four channels on the transmitting VSC7217 (the 4 Tn(7:0) busses) is viewed as a 32-bit word, then the receiv-

ing VSC7217 will recover an identical word. For example, if a transmit pattern was ‘ABCD’, ‘EFGH’, ‘IJKL’,

etc., the receiver should not recover data words as ‘ABGD’, ‘EFKH’, ‘IJOL’, etc. This requires the four trans-

mit channels to obtain input data on a common clock (TMODE(2:0)=000 or 1X0) and the four receive channels

to present output data on a common word clock (RMODE(1:0)=0X or 10).

There are elastic buffers within the receiver used to deskew the four channels and align them to a common

word clock. An elastic buffer allows the channels’ input to be skewed up to ±6 bit times (12 bit times total skew

between any two channels) to accommodate circuit imperfections, differences in transmission delay and jitter.

Multiple VSC7217 devices can also be used in synchronous operation if the skew between all serial input pairs

is maintained less than ±6 serial clock bit times. This allows easy implementation of robust systems and is dis-

cussed in greater detail in the Using Multiple VSC7217s in Parallel section.

In order to perform word alignment, a synchronization point must be seen across all aligned receive chan-

nels within the ±6 bit time window. The VSC7217 receiver recognizes the first four characters of the Word

Sync Sequence (either K28.5+ K28.5+ K28.5- K28.5- or K28.5- K28.5- K28.5+ K28.5+) as the synchronization

point. As a model for understanding, consider the case where a VSC7217 transmitter sends 32 bits of data to the

receiver via copper media, which has small cable length differences, causing a channel-to-channel skew. All

transmit channels that are to be word-aligned transmit the Word Sync Sequence in parallel. On detection of the

synchronization point, the receivers will reposition the recovered data within their elastic buffers in order to

align all four channels and remove any channel-to-channel skew. All normal data characters following the

G52325-0, Rev. 3.0

6/14/00

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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