VSC8117 查看數據表（PDF） - Vitesse Semiconductor

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VSC8117

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery

Vitesse Semiconductor 

Data Sheet

VSC8117

VITESSE

SEMICONDUCTOR CORPORATION

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

Table 7: Receive Data Output Timing Table (STS-3 Operation)

Parameter

Description

Min

TRXCLKIN Receive clock period

-

TRXLSCKT Receive data output byte clock period

-

TRXVALID

Time data on RXOUT [7:0] and FP is valid before and

after the rising edge of RXLSCKOUT

22

TPW

Pulse width of frame detection pulse FP

-

Typ

6.43

51.44

-

51.44

Max

-

-

-

-

Units

ns

ns

ns

ns

Data Latency

The VSC8117 contains several operating modes, each of which exercise different logic paths through the

part. Table 10 bounds the data latency through each path with an associated clock signal.

Table 8: Data Latency

Circuit Mode

Description

Receive

Facilities

Loopback

MSB at RXDATAIN to data on RXOUT [7:0]

MSB at RXDATAIN to MSB at TXDATAOUT

Clock

Reference

RXCLKIN

RXCLKIN

Range of Clock

cycles

25-35

2-4

Clock Recovery Unit

Table 9: Reference Frequency for the CRU

CRUREFSEL

1

1

0

STS12

CRUREFCLK

Frequency

[MHz]

Output

Frequency

[MHz]

1

77.76 ± 500ppm

622.08

0

77.76 ± 500ppm

155.52

Uses CMU’s Reference Clock (See Table 10 below)

Clock Multiplier Unit

Table 10: Reference Frequency Selection and Output Frequency Control

STS12

1

1

0

0

CMUFREQSEL

1

0

1

0

Reference

Frequency

[MHz]

19.44

77.76

19.44

77.76

Output

Frequency

[MHz]

622.08

622.08

155.52

155.52

G52221-0, Rev. 4.1

1/8/00

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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