W77E516 查看數據表（PDF） - Winbond

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W77E516

8-BIT MICROCONTROLLER

Winbond 

Preliminary W77E516

Status Register

Bit:

7

-

6

5

4

3

2

1

0

HIP

LIP XTUP SPTA1 SPRA1 SPTA0 SPRA0

Mnemonic: STATUS

Address: C5h

HIP: High Priority Interrupt Status. When set, it indicates that software is servicing a high priority

interrupt. This bit will be cleared when the program executes the corresponding RETI

instruction.

LIP: Low Priority Interrupt Status. When set, it indicates that software is servicing a low priority

interrupt. This bit will be cleared when the program executes the corresponding RETI

instruction.

XTUP: Crystal Oscillator Warm-up Status. When set, this bit indicates CPU has detected clock to

be ready. Each time the crystal oscillator is restarted by exit from power down mode,

hardware will clear this bit. This bit is set to 1 after a power-on reset.

SPTA1: Serial Port 1 Transmit Activity. This bit is set during serial port 1 is currently transmitting

data. It is cleared when TI_1 bit is set by hardware. Changing the Clock Divide Control bits

CD0, CD1 will be ignored when this bit is set to 1 and SWB = 1.

SPRA1: Serial Port 1 Receive Activity. This bit is set during serial port 1 is currently receiving a

data. It is cleared when RI_1 bit is set by hardware. Changing the Clock Divide Control bits

CD0, CD1 will be ignored when this bit is set to 1 and SWB = 1.

SPTA0: Serial Port 0 Transmit Activity. This bit is set during serial port 0 is currently transmitting

data. It is cleared when TI bit is set by hardware. Changing the Clock Divide Control bits

CD0, CD1 will be ignored when this bit is set to 1 and SWB = 1.

SPRA0: Serial Port 0 Receive Activity. This bit is set during serial port 0 is currently receiving a

data. It is cleared when RI bit is set by hardware. Changing the Clock Divide Control bits

CD0, CD1 will be ignored when this bit is set to 1 and SWB = 1.

NVM Address Select

Bit:

7

6

5

4

3

2

1

0

-

-

DCID5 DCID4 DCID3 DCID2 DCID1 DCID0

Address: C6h

Mnemonic: NVMSEL

DCID[5:0]: 6-bit address to access individual location of on-chip 64 bytes non-volatile data memory.

For instance, asserting DCID[5:0] = 00000b addresses to the NVM 1st byte, DCID[5:0] =

11111b addresses to the NVM 64th byte.

NVM ADDRESS 0 1 2 3 4 5 6 7 … 63

DCID5

0 0 0 0 0 0 0 0…1

DCID4

0 0 0 0 0 0 0 0…1

DCID3

0 0 0 0 0 0 0 0…1

DCID2

0 0 0 0 1 1 1 1…1

DCID1

0 0 1 1 0 0 1 1…1

DCID0

0 1 0 1 0 1 0 1…1

- 27 -

Publication Release Date: August 16, 2002

Revision A1

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