PSD834F2-10J 查看數據表（PDF） - STMicroelectronics
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PSD834F2-10J
STMicroelectronics
PSD834F2-10J Datasheet PDF : 95 Pages
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PSD834F2V
Table 5. I/O Port Latched Address Output Assignments (Note 1)
MCU
Port A
Port A (3:0)
Port A (7:4)
Port B
Port B (3:0)
Port B (7:4)
8051XA (8-bit)
N/A
Address a7-a4
Address a11-a8 N/A
80C251 (page mode)
N/A
N/A
Address a11-a8 Address a15-a12
All other 8-bit multiplexed
Address a3-a0
Address a7-a4
Address a3-a0
Address a7-a4
8-bit non-multiplexed bus
N/A
N/A
Address a3-a0
Address a7-a4
Note: 1. See the section entitled “I/O PORTS”, on page 46, on how to enable the Latched Address Output function.
2. N/A = Not Applicable
Table 6. Register Address Offset
Register Name Port A Port B Port C Port D Other1
Description
Data In
00
01
10
11
Reads Port pin as input, MCU I/O input mode
Control
02
03
Selects mode between MCU I/O or Address Out
t(s) Data Out
04
05
12
13
Stores data for output to Port pins, MCU I/O output
mode
c Direction
06
07
14
15
Configures Port pin as input or output
rodu Drive Select
08
09
16
17
Configures Port pins as either CMOS or Open
Drain on some pins, while selecting high slew rate
on other pins.
P Input Macrocell
0A
0B
18
Reads Input Macrocells
lete Enable Out
0C
0D
1A
1B
Reads the status of the output enable to the I/O
Port driver
so Output Macrocells
b AB
20
20
READ – reads output of macrocells AB
WRITE – loads macrocell flip-flops
O Output Macrocells
- BC
21
21
READ – reads output of macrocells BC
WRITE – loads macrocell flip-flops
t(s) Mask Macrocells AB 22
22
Blocks writing to the Output Macrocells AB
c Mask Macrocells BC
23
23
Blocks writing to the Output Macrocells BC
du Primary Flash
ro Protection
C0
Read only – Primary Flash Sector Protection
P Secondary Flash
memory Protection
C2
Read only – PSD Security and Secondary Flash
memory Sector Protection
te JTAG Enable
C7
Enables JTAG Port
ole PMMR0
B0
Power Management Register 0
bsPMMR2
B4
Power Management Register 2
OPage
E0
Page Register
VM
E2
Places PSD memory areas in Program and/or
Data space on an individual basis.
Note: 1. Other registers that are not part of the I/O ports.
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