PSD834F2-10J 查看數據表（PDF） - STMicroelectronics

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PSD834F2-10J

Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM

STMicroelectronics 

PSD834F2V

DETAILED OPERATION

As shown in Figure 2, the PSD consists of six ma- the primary Flash memory has a Select signal

jor types of functional blocks:

(FS0-FS7) which can contain up to three product

■ Memory Blocks

■ PLD Blocks

■ MCU Bus Interface

terms. Each of the four sectors of the secondary

Flash memory has a Select signal (CSBOOT0-

CSBOOT3) which can contain up to three product

terms. Having three product terms for each Select

■ I/O Ports

signal allows a given sector to be mapped in differ-

■ Power Management Unit (PMU)

■ JTAG Interface

ent areas of system memory. When using a MCU

with separate Program and Data space, these

flexible Select signals allow dynamic re-mapping

The functions of each block are described in the of sectors from one memory space to the other.

following sections. Many of the blocks perform

multiple functions, and are user configurable.

Ready/Busy (PC3). This signal can be used to

output the Ready/Busy status of the PSD. The out-

put on Ready/Busy (PC3) is a 0 (Busy) when Flash

memory is being written to, or when Flash memory

MEMORY BLOCKS

is being erased. The output is a 1 (Ready) when

no WRITE or Erase cycle is in progress.

The PSD has the following memory blocks:

– Primary Flash memory

t(s) – Secondary Flash memory

– SRAM

c The Memory Select signals for these blocks origi-

u nate from the Decode PLD (DPLD) and are user-

rod defined in PSDsoft Express.

Primary Flash Memory and Secondary Flash

P memory Description

te The primary Flash memory is divided evenly into

le eight equal sectors. The secondary Flash memory

is divided into four equal sectors. Each sector of

so either memory block can be separately protected

b from Program and Erase cycles.

O Flash memory may be erased on a sector-by-sec-

- tor basis. Flash sector erasure may be suspended

) while data is read from other sectors of the block

t(s and then resumed after reading.

During a Program or Erase cycle in Flash memory,

uc the status can be output on Ready/Busy (PC3).

d This pin is set up using PSDsoft Express Configu-

ro ration.

Memory Block Select Signals

P The DPLD generates the Select signals for all the

te internal memory blocks (see the section entitled

Obsole “PLDS”, on page 27). Each of the eight sectors of

Memory Operation. The primary Flash memory

and secondary Flash memory are addressed

through the MCU Bus Interface. The MCU can ac-

cess these memories in one of two ways:

■ The MCU can execute a typical bus WRITE or

READ operation just as it would if accessing a

RAM or ROM device using standard bus cycles.

■ The MCU can execute a specific instruction that

consists of several WRITE and READ

operations. This involves writing specific data

patterns to special addresses within the Flash

memory to invoke an embedded algorithm.

These instructions are summarized in Table 7.

Typically, the MCU can read Flash memory using

READ operations, just as it would read a ROM de-

vice. However, Flash memory can only be altered

using specific Erase and Program instructions. For

example, the MCU cannot write a single byte di-

rectly to Flash memory as it would write a byte to

RAM. To program a byte into Flash memory, the

MCU must execute a Program instruction, then

test the status of the Program cycle. This status

test is achieved by a READ operation or polling

Ready/Busy (PC3).

Flash memory can also be read by using special

instructions to retrieve particular Flash device in-

formation (sector protect status and ID).

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