M66258FP 查看數據表（PDF） - Renesas Electronics

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M66258FP

8192 × 8-Bit Line Memory

Renesas Electronics 

M66258FP

n-bit Delay 2

(Slides input timings of WRES and RRES at cycles according to the delay length)

WCK

RCK

0 cycle 1 cycle 2 cycle n − 2 cycle n − 1 cycle n cycle n + 1 cycle n + 2 cycle n + 3 cycle

tRESS tRESH

WRES

tRESS tRESH

RRES

tDS tDH

tDS tDH

Dn

(0)

(1)

(2)

(n − 2)

(n − 1)

(n)

(n + 1)

(n + 2)

(n + 3)

m cycle

tAC

tOH

Qn

(0)

(1)

(2)

(3)

WE, RE = "L"

n-bit Delay 3

(Slides address by disabling RE in the period according to the delay length)

WCK

RCK

0 cycle 1 cycle 2 cycle

tRESS tRESH

WRES

RRES

RE

tDS tDH

Dn

(0)

(1)

(2)

HIGH-Z

Qn

m cycle

n − 1 cycle n cycle n + 1 cycle n + 2 cycle n + 3 cycle

tNREH tRES

tDS tDH

(n − 2)

(n − 1)

(n)

(n + 1)

(n + 2)

(n + 3)

tAC

tOH

(0)

(1)

(2)

(3)

WE, RE = "L"

m≥3

REJ03F0252-0200 Rev.2.00 Sep 14, 2007

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