M68Z512 查看數據表（PDF） - STMicroelectronics

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M68Z512

4 Mbit (512 Kbit x 8) Low Power SRAM with Output Enable

STMicroelectronics 

M68Z512

Table 5. DC Characteristics

Symbol

Parameter

Test Condition(1)

Min

Typ

ILI Input Leakage Current

0V ≤ VIN ≤ VCC

ILO Output Leakage Current

0V ≤ VOUT ≤ VCC

ICC1(2) Supply Current

VCC = 3.6V

ICC2(3)

Supply Current (Standby)

TTL

VCC = 3.6V, E = VIH

ICC3(4)

Supply Current (Standby)

CMOS

VCC = 3.6V, E ≥ VCC – 0.3V, f = 0

1.6

VIL Input Low Voltage

–0.3

VIH Input High Voltage

2.2

VOL Output Low Voltage

IOL = 2.1mA

VOH Output High Voltage

IOH = –1mA

2.4

Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V (except where noted).

2. Average AC current, Outputs open, cycling at tAVAV minimum.

3. All other Inputs at VIL ≤ 0.8V or VIH ≥ 2.2V.

4. All other Inputs at VIL ≤ 0.3V or VIH ≥ VCC –0.3V.

Max Unit

±1

µA

±1

µA

90

mA

15

mA

20

µA

0.8

V

VCC + 0.3 V

0.4

V

V

OPERATION

The M68Z512 has a Chip Enable power down fea-

ture which invokes an automatic standby mode

whenever Chip Enable is de-asserted (E = High).

An Output Enable (G) signal provides a high

speed tri-state control, allowing fast READ/WRITE

Table 6. Operating Modes

Operation

E

W

Read

VIL

VIH

Read

VIL

VIH

Write

VIL

VIL

Deselect

Note: X = VIH or VIL.

VIH

X

Cycles to be achieved with the common I/O data

bus. Operational modes are determined by device

control inputs W and E as summarized in the Op-

erating Modes table (see Table 6).

G

DQ0-DQ7

VIH

Hi-Z

VIL

Data Output

X

Data Input

X

Hi-Z

Power

Active

Active

Active

Standby

6/15

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