LF3320QC12 查看數據表（PDF） - LOGIC Devices
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LF3320QC12 Datasheet PDF : 24 Pages
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DEVICES INCORPORATED
LF3320
Horizontal Digital Image Filter
TABLE 2. CONFIGURATION REGISTER 0 – ADDRESS 200H
BITS FUNCTION
DESCRIPTION
0
ALU Mode Filter A
0: A + B
1: B – A
1
Pass A Filter A
0 : ALU Input A = 0
1 : ALU Input A = Forward Register Path
2
Pass B Filter A
0 : ALU Input B = 0
1 : ALU Input B = Reverse Register Path
11-3 Reserved
Should be set to “0”
TABLE 3. CONFIGURATION REGISTER 1 – ADDRESS 201H
BITS FUNCTION
DESCRIPTION
0
Filter A Odd-Tap
Interleave Mode
0 : Odd-Tap Interleave Mode Disabled
1 : Odd-Tap Interleave Mode Enabled
4-1
Filter A I/D Register Length 0000 :
0001 :
0010 :
0011 :
0100 :
0101 :
0110 :
0111 :
1000 :
1001 :
1010 :
1011 :
1100 :
1101 :
1110 :
1111 :
1 Register
2 Registers
3 Registers
4 Registers
5 Registers
6 Registers
7 Registers
8 Registers
9 Registers
1 0 Registers
1 1 Registers
1 2 Registers
1 3 Registers
1 4 Registers
1 5 Registers
1 6 Registers
5
Filter A Tap Number
0 : Even Number of Taps
1 : Odd Number of Taps
6
Filter A Data Reversal
0 : Data Reversal Enabled
1 : Data Reversal Disabled
11-7 Reserved
Should be set to “0”
I/D Register Data Path Control
The three multiplexers in the I/D
Register data path control how data
is routed through the forward and
reverse data paths.
The forward data path contains the
I/D Registers in which data flows
from left to right in the block diagram
in Figure 1. The reverse data path
contains the I/D Registers in which
data flows from right to left.
In Single or Dual Filter Modes, data
is fed from the forward data path to
the reverse data path as follows.
When the filter is configured for an
even number of taps, data from the
last I/D Register in the forward data
path is fed into the first I/D Register
in the reverse data path (see Figure 13).
When the filter is configured for an
odd number of taps, the data which
will appear at the output of the last
I/D Register in the forward data
path on the next clock cycle is fed
into the first I/D Register in the
reverse data path. Bit 5 in Configu-
ration Register 1 and Configuration
Register 3 configures Filters A and B
respectively for an even or odd
number of taps.
When interleaved data is fed through
the device and an even tap filter is
desired, the filter should be configured
for an even number of taps and the I/D
Register length should match the
number of data sets interleaved together.
When interleaved data is fed through
the device and an odd tap filter is
desired, the filter should be set to
Odd-Tap Interleave Mode. Bit 0 of
Configuration Register 1 and Configura-
tion Register 3 configures Filters A and
B respectively for Odd-Tap Interleave
Mode. When the filter is configured for
Odd-Tap Interleave Mode, data from the
next to last I/D Register in the forward
data path is fed into the first I/D
Register in the reverse data path.
When the filter is configured for an odd
number of taps (interleaved or
non-interleaved modes), the filter is
structured such that the center data
value is aligned simultaneously at the A
and B inputs of the last ALU in the
forward data path. In order to achieve
the correct result, the user must divide
the coefficient by two.
Data Reversal
Data reversal circuitry is placed after the
multiplexers which route data from the
forward data path to the reverse data
path (see Figure 14). When decimating,
the data stream must be reversed in
order for data to be properly aligned at
the inputs of the ALUs.
When data reversal is enabled, the
circuitry uses a pair of LIFOs to reverse
the order of the data sent to the reverse
data path. TXFRA and TXFRB control
the LIFOs in Filters A and B respectively.
When TXFRA/TXFRB goes LOW, the
LIFO sending data to the reverse data
path becomes the LIFO receiving data
from the forward data path, and the LIFO
receiving data from the forward data
path becomes the LIFO sending data to
Video Imaging Products
2-11
08/16/2000–LDS.3320-N
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