AS3843N13 查看數據表（PDF） - Astec Semiconductor => Silicon Link
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AS3843N13 Datasheet PDF : 20 Pages
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Current Mode Controller
AS384x
charged via resistor (R) from the rectified AC line.
When the voltage on the capacitor (VCC) reaches
the upper UVLO threshold, the IC (and hence, the
power supply) turns on and the voltage on C
begins to quickly discharge due to the increased
operating current. During this time, the auxiliary
winding begins to supply the current necessary to
run the IC. The capacitor must be sufficiently large
to maintain a voltage greater than the lower UVLO
threshold during start-up. The value of R must be
selected to provide greater than 1 mA of current at
the minimum DC bus voltage (R < VDCmin/1 mA).
The UVLO feature of the AS3842 has significant
advantages over standard 3842 devices. First,
the UVLO thresholds are based on a temperature
compensated bandgap reference rather than con-
ventional zeners. Second, the UVLO disables the
output at power down, offering additional protec-
tion in cases where VREG is heavily decoupled.
The UVLO on some 3842 devices shuts down the
5 volt regulator only, which results in eventual
power down of the output only after the 5 volt rail
collapses. This can lead to unwanted stresses on
the switching devices during power down. The
AS3842 has two separate comparators which
monitor both VCC and VREF and hold the output
low if either are not within specification.
The AS3842 family offers two different UVLO
options. The AS3842/4 has UVLO thresholds of
16 volts (on) and 10 volts (off). The AS3843/5 has
UVLO levels of 8.4 volts (on) and 7.6 volts (off).
1.2 Reference (VREG and VFB)
The AS3842 effectively has two precise bandgap
based temperature compensated voltage refer-
ences. Most obvious is the VREG pin (pin 8) which
is the output of a series pass regulator. This 5.0 V
output is normally used to provide charging cur-
rent to the oscillatorÕs timing capacitor (Section
1.3). In addition, there is a trimmed internal 2.5 V
reference which is connected to the non-inverting
(+) input of the error amplifier. The tolerance of
the internal reference is ± 1% over the full speci-
fied temperature range, and ± 1% for VREG.
The reference section of the AS3842 is greatly
improved over the standard 3842 in a number of
ways. For example, in a closed loop system, the
voltage at the error amplifierÕs inverting input (VFB,
pin 1) is forced by the loop to match the voltage at
the non-inverting input. Thus, VFB is the voltage
which sets the accuracy of the entire system. The
2.5 V reference of the AS3842 is tightly trimmed
for precision at VFB, including errors caused by
the op amp, and is specified over temperature.
This method of trim provides a precise reference
voltage for the error amplifier while maintaining
the original 5 V regulator specifications. In addi-
tion, force/sense (Kelvin) bonding to the package
pin is utilized to further improve the 5 V load reg-
ulation. Standard 3842s, on the other hand, spec-
ify tight regulation for the 5 V output only and rate
it over line, load and temperature. The voltage at
VFB, which is of critical importance, is loosely
specified and only at 25¡C.
The reference section, in addition to providing a
precise DC reference voltage, also powers most
of the ICÕs internal circuitry. Switching noise,
therefore, can be internally coupled onto the ref-
erence. With this in mind, all of the logic within
the AS3842 was designed with ECL type circuitry
which generates less switching noise because it
runs at essentially constant current regardless of
logic state. This, together with improved AC noise
rejection, results in substantially less switching
noise on the 5 V output.
The reference output is short circuit protected
and can safely deliver more than 20 mA to power
external circuitry.
1.3 Oscillator
The newly designed oscillator of the AS3842 is
enhanced to give significantly improved perfor-
mance. These enhancements are discussed in
ASTEC Semiconductor
11
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