ISL85410 查看數據表（PDF） - Renesas Electronics

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ISL85410

Wide VIN 1A Synchronous Buck Regulator

Renesas Electronics 

ISL85410

Buck Regulator Output Capacitor Selection

An output capacitor is required to filter the inductor current. The

current mode control loop allows the use of low ESR ceramic

capacitors and thus supports very small circuit implementations

on the PC board. Electrolytic and polymer capacitors may also be

used.

While ceramic capacitors offer excellent overall performance

and reliability, the actual in-circuit capacitance must be

considered. Ceramic capacitors are rated using large

peak-to-peak voltage swings and with no DC bias. In the DC/DC

converter application, these conditions do not reflect reality. As a

result, the actual capacitance may be considerably lower than

the advertised value. Consult the manufacturers data sheet to

determine the actual in-application capacitance. Most

manufacturers publish capacitance vs DC bias so that this effect

can be easily accommodated. The effects of AC voltage are not

frequently published, but an assumption of ~20% further

reduction will generally suffice. The result of these

considerations may mean an effective capacitance 50% lower

than nominal and this value should be used in all design

calculations. Nonetheless, ceramic capacitors are a very good

choice in many applications due to their reliability and extremely

low ESR.

The following equations allow calculation of the required

capacitance to meet a desired ripple voltage level. Additional

capacitance may be used.

For the ceramic capacitors (low ESR):

VOUTripple=

--------------------I----------------

8 fS W CO U T

(EQ. 6)

Where I is the inductor’s peak-to-peak ripple current, fSW is the

switching frequency and COUT is the output capacitor.

If using electrolytic capacitors then:

VOUTripple= I*ESR

(EQ. 7)

Loop Compensation Design

When COMP is not connected to VCC, the COMP pin is active for

external loop compensation. The ISL85410 uses constant

frequency peak current mode control architecture to achieve a

fast loop transient response. An accurate current sensing pilot

device in parallel with the upper MOSFET is used for peak current

control signal and overcurrent protection. The inductor is not

considered as a state variable since its peak current is constant,

and the system becomes a single order system. It is much easier

to design a type II compensator to stabilize the loop than to

implement voltage mode control. Peak current mode control has

an inherent input voltage feed-forward function to achieve good

line regulation. Figure 47 shows the small signal model of the

synchronous buck regulator.

^iin

V^in

+

ILd^ 1:D Vind^

^iL LP

RLP

RT

vo^

Rc

Ro

Co

d^

Ti(S)

K

Fm

+

He(S)

Tv(S)

V^comp -Av(S)

FIGURE 47. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK

REGULATOR

Vo

R2

C3

VFB

-

VCOMP

VREF

GM

R3

+

R6

C7

C6

FIGURE 48. TYPE II COMPENSATOR

Figure 48 shows the type II compensator and its transfer function

is expressed as shown in Equation 8:

AvS= v-ˆ---C-v-ˆ--O-F---BM-----P-- = ---C-----6----+-----C-G---7--M----------R-R---3-2-----+-----R----3---- -S-----1--1---+--+---------------cS------cS---z------p---1-----1--------1--1---+--+---------------c-S-----c--S-z------p---2------2-----

(EQ. 8)

Where,

cz1 = -R----6--1-C-----6- , cz2 = -R----2--1-C-----3- cp1= R--C---6-6---C--+--6--C-C----7-7- cp2= C--R---3-2--R---+--2--R-R----3-3-

Compensator design goal:

High DC gain

Choose loop bandwidth fc less than 100kHz

Gain margin: >10dB

Phase margin: >40°

The compensator design procedure is as follows:

The loop gain at crossover frequency of fc has a unity gain.

Therefore, the compensator resistance R6 is determined by

Equation 9.

FN8375 Rev 7.00

March 13, 2015

Page 17 of 21

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