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ISL85410 查看數據表(PDF) - Renesas Electronics

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ISL85410
Renesas
Renesas Electronics Renesas
ISL85410 Datasheet PDF : 21 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
ISL85410
R6 = 2-----G---f--Mc---V----o--V--C--F--o--B--R----t = 22.75103 fcVoCo
60
(EQ. 9)
45
Where GM is the transconductance, gm, of the voltage error
amplifier in each phase. Compensator capacitor C6 is then given
30
by Equation 10.
C6 = R----R-o---C-6----o- = -V-I--o-o--R-C----6-o- ,C7= max(R----R-c---C-6----o-,----f--S----1W-----R-----6-)
(EQ. 10)
15
0
Put one compensator pole at zero frequency to achieve high DC
gain, and put another compensator pole at either ESR zero
-15
frequency or half switching frequency, whichever is lower in
Equation 10. An optional zero can boost the phase margin. CZ2
-30
is a zero due to R2 and C3
100
1k
10k
100k
1M
Put compensator zero 2 to 5 times fc.
FREQUENCY (Hz)
C3= ----f--c-1--R-----2-
(EQ. 11)
180
150
Example: VIN = 12V, VO = 5V, IO = 1A, fSW = 500kHz,
R2 = 90.9kΩ, Co = 22µF/5mΩ, L = 39µH, fc = 50kHz, then
120
compensator resistance R6:
90
R6 = 22.75103 50kHz 5V 22F = 125.12k
(EQ. 12)
60
It is acceptable to use 124kΩas theclosest standard value for
R6.
C6 = -1-5--A--V-------1--2-2--2-4----k---F---- = 0.88nF
(EQ. 13)
30
0
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 49. SIMULATED LOOP GAIN
C7= max(-5---m----1---2---4----k-2---2--------F--,--------5----0---0----k---H---1--z--------1---2---4----k-------)= (0.88pF,5.1pF)
(EQ. 14)
It is also acceptable to use the closest standard values for C6 and
C7. There is approximately 3pF parasitic capacitance from VCOMP
to GND; Therefore, C7 is optional. Use C6 = 1500pF and
C7 = OPEN.
C3= --------5----0---k----H-----z1-------9----0---.--9---k------- = 70pF
(EQ. 15)
Use C3 = 68pF. Note that C3 may increase the loop bandwidth
from previous estimated value. Figure 49 shows the simulated
voltage loop gain. It is shown that it has a 75kHz loop bandwidth
with a 61° phase margin and 6dB gain margin. It may be more
desirable to achieve an increased gain margin. This can be
accomplished by lowering R6 by 20% to 30%. In practice,
ceramic capacitors have significant derating on voltage and
temperature, depending on the type. Please refer to the ceramic
capacitor datasheet for more details.
FN8375 Rev 7.00
March 13, 2015
Page 18 of 21

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