CXD1852Q 查看數據表（PDF） - Sony Semiconductor

零件编号

产品描述 (功能)

生产厂家

CXD1852Q

MPEG1 Decoder

Sony Semiconductor 

CXD1852Q

Pin No. Symbol

I/O

Description

92 HSYNC

Horizontal sync signal. When using the built-in sync generator, the dot

I/O clock (DCLK) is frequency divided and output. When not using the sync

generator, this pin is an input.

93 VSYNC

Vertical sync signal. When using the built-in sync generator, the dot clock

I/O (DCLK) is frequency divided and output. When not using the built-in sync

generator, this pin is an input.

Field identification signal (FID) and horizontal sync phase reference signal

(FHREF). The signal to be used is set in the register. When set to FID, this

pin is an output if using the built-in sync generator, and an input if not

94 FID/FHREF I/O using the built-in sync generator. High corresponds to odd fields. When set

to FHREF, this pin outputs the signal obtained by frequency dividing XTL0.

When XTL0 is 8fsc, this signal is equivalent to the HSYNC cycle, and can

be used for phase comparison with the HSYNC signal.

95

CBLNK/

FSC

Composite blanking signal (CBLNK) and fsc signal. The signal to be used

is set in the register. When set to CBLNK, this pin is an output if using the

I/O built-in sync generator, and an input if not using the built-in sync generator.

When set to fsc, this pin outputs the signal obtained by frequency dividing

XTL0. The frequency division ratio can be selected from 1/8 or 1/16.

96 CSYNC

O

Composite sync signal obtained by frequency dividing DCLK. This pin

cannot be input.

97 XSGRST

I

Sync generator reset signal input. The built-in sync generator is initialized

by setting this pin low.

98 CLK0O

O

Output for clock obtained by frequency dividing XTL0. The frequency

division ratio can be selected from 1, 1/2, 1/4 or 1/8.

99 DOUT

O Audio digital output.

100 DATO

O Audio serial data output to DAC.

101 LRCO

O L/R clock output to DAC.

102 BCKO

O Bit clock output to DAC.

103 FSXI

I

Audio interface clock input. Input 256fs (11.2896MHz), 384fs

(16.9344MHz), 512fs (22.5792MHz), or 768fs (33.8688MHz), etc.

106 XTL2O

107 XTL2I

O Master clock for CD-ROM and audio decoders. Input the clock to XTL2I or

connect an oscillator between XTL2I and XTL2O. The recommended

frequency is 45MHz. Note that this clock is for the internal circuits, and the

I input and output are not synchronized.

109 C2PO

I

C2 pointer input from CD-DSP. Indicates that the DATI input contains an

error.

110 LRCI

I LR clock input from CD-DSP. Indicates the L or R channel of DATI.

111 DATI

I Serial data input from CD-DSP.

112 BCKI

I Bit clock input from CD-DSP. This clock strobes the DATI input.

113 DOIN

I Digital data input from CD-DSP.

114 XHCS

I Chip select signal input during register access.

115 XHDT

Wait signal output during register access. This pin is valid only when the

I/O

host interface operates in parallel mode. This pin functions as an open

drain, and should therefore be pulled up. It should be pulled up when the

host interface operates in serial mode as well.

–4–

Share Link: