VSC9142 查看數據表（PDF） - Vitesse Semiconductor

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VSC9142

STS-48c Packet/ATM Over SONET/SDH Device With Integrated Mux/Demux and Clock and Data Recovery

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

VSC9142

STS-48c Packet/ATM Over SONET/SDH Device

With Integrated Mux/Demux and Clock and Data Recovery

• Line loopback is supported by looping the output from the Recieve Line Overhead Processor (RLOP) in

the receive direction back to the input of the Transmit Line Overhead Processor (TLOP), in the transmit

direction.

• Drop side loopback is supported by looping the output from the Tx FIFO to the input of the Rx FIFO.

This loopback is supported for both packet and ATM cell mode.

G52319-0, Rev. 3.1

6/12/00

 VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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