F81865F 查看數據表（PDF） - Feature Integration Technology Inc.
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F81865F Datasheet PDF : 128 Pages
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F81865
IRQ Share Register ⎯ Index F0h
Bit
Name
R/W Default
Description
7 UR4_9BIT_MODE R/W
6 UR4_AUTO_ADDR R/W
0: normal UART function
0 1: enable 9-bit mode (multi-drop mode).
In the 9-bit mode, the parity bit becomes the address/data bit.
This bit works only in 9-bit mode.
0: the SM2 bit will be cleared by host, so that data could be received.
0 1: the SM2 bit will be cleared by hardware according to the sent address and
the given address (or broadcast address derived by SADDR_UR4 and
SADEN_UR4)
5 UR4_RS485_INV R/W 0 Invert RTS# if UR4_RS485_EN is set.
0: RS232 driver.
4 UR4_RS485_EN R/W 0 1: RS485 driver. Auto drive RTS# high when transmitting data, otherwise
is kept low.
3-2
Reserved
-
- Reserved.
1 UR4IRQ_MODE R/W
0 UR4IRQ_SHARE R/W
Clock Register ⎯ Index F2h
0 : PCI IRQ sharing mode.
0 1 : ISA IRQ sharing mode.
This bit is effective in IRQ sharing mode.
0 : IRQ is not sharing with other device.
0 1 : IRQ is sharing with other device.
Bit
Name
R/W Default
Description
7-2
Reserved
-
- Reserved.
Select the clock source for UART4.
00: 1.8432MHz.
1-0 UR4_CLK_SEL R/W 00b 01: 18.432MHz.
10: 24MHz.
11: 14.769MHz.
9bit-mode Slave Address Register ⎯ Index F4h
Bit
Name
R/W Default
Description
This byte accompanying with SADEN_UR4 will determine the given address
and broadcast address in 9-bit mode. The UART will response to both given
and broadcast address.
Follow the description to determine the given address and broadcast address:
13. given address: If bit n of SADEN_UR4 is “0”, then the corresponding bit of
SADDR_UR4 is don’t care.
14. broadcast address: If bit n of ORed SADDR_UR4 and SADEN_UR4 is “0”,
7-0
SADDR_UR4 R/W 00h
don’t care that bit. The remaining bit which is “1” is compared to the
received address.
Ex.
SADDR_UR4
0101_1100b
SADEN_UR4
Given Address
Broadcast Address
1111_1001b
0101_1xx0b
1111_11x1b
114
May, 2010
V0.28P
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