DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

F81865F 查看數據表(PDF) - Feature Integration Technology Inc.

零件编号
产品描述 (功能)
生产厂家
F81865F
FINTEK
Feature Integration Technology Inc. FINTEK
F81865F Datasheet PDF : 128 Pages
First Prev 111 112 113 114 115 116 117 118 119 120 Next Last
9bit-mode Slave Address Mask Register Index F5h
Bit
Name
R/W Default
Description
F81865
This byte accompanying with SADDR_UR4 will determine the given address
and broadcast address in 9-bit mode. The UART_UR4 will response to both
given and broadcast address.
Follow the description to determine the given address and broadcast address:
15. given address: If bit n of SADEN_UR4 is “0”, then the corresponding bit of
SADDR_UR4 is don’t care.
16. broadcast address: If bit n of ORed SADDR_UR4 and SADEN_UR4 is “0”,
7:0
SADEN_UR4 R/W 00h
don’t care that bit. The remaining bit which is “1” is compared to the
received address.
Ex.
SADDR_UR4
0101_1100b
SADEN_UR4
1111_1001b
Given Address
0101_1xx0b
Broadcast Address
1111_11x1b
8.15 UART5 Registers (CR14)
UART 5 Device Enable Register Index 30h
Bit
Name
R/W Default
Description
7-1
Reserved
-
- Reserved
0: disable UART 5.
0
UR5_EN
R/W 0
1: enable UART 5.
Base Address High Register Index 60h
Bit
Name
R/W Default
Description
7-0 BASE_ADDR_HI R/W 00h The MSB of UART 5 base address.
Base Address Low Register Index 61h
Bit
Name
R/W Default
Description
7-0 BASE_ADDR_LO R/W 00h The LSB of UART 5 base address.
IRQ Channel Select Register Index 70h
Bit
Name
R/W Default
Description
7-4
Reserved
-
- Reserved.
3-0
SELUR5IRQ
R/W 3h Select the IRQ channel for UART 5.
IRQ Share Register Index F0h
Bit
Name
R/W Default
Description
0: normal UART function
7 UR5_9BIT_MODE R/W 0 1: enable 9-bit mode (multi-drop mode).
In the 9-bit mode, the parity bit becomes the address/data bit.
6 UR5_AUTO_ADDR R/W
This bit works only in 9-bit mode.
0: the SM2 bit will be cleared by host, so that data could be received.
0 1: the SM2 bit will be cleared by hardware according to the sent address and
the given address (or broadcast address derived by SADDR_UR5 and
SADEN_UR5)
5 UR5_RS485_INV R/W 0 Invert RTS# if UR5_RS485_EN is set.
0: RS232 driver.
4 UR5_RS485_EN R/W 0 1: RS485 driver. Auto drive RTS# high when transmitting data, otherwise
is kept low.
115
May, 2010
V0.28P

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]