F81865F 查看數據表（PDF） - Feature Integration Technology Inc.
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F81865F Datasheet PDF : 128 Pages
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F81865
0 : Full Duplex function for IR self test.
2
HDUPLX
R/W 0 1 : Half Duplex function.
Return 1 when read.
1
TXINV_IR
R/W
0
RXINV_IR
R/W
Clock Register ⎯ Index F2h
0 : IRTX is not inversed.
0
1 : Inverse the IRTX.
0 : IRRX is not inversed.
0 1 : Inverse the IRRX.
Bit
Name
R/W Default
Description
7-2
Reserved
-
- Reserved.
Select the clock source for UART6.
00: 1.8432MHz.
1-0 UR6_CLK_SEL R/W 00b 01: 18.432MHz.
10: 24MHz.
11: 14.769MHz.
9bit-mode Slave Address Register ⎯ Index F4h
Bit
Name
R/W Default
Description
This byte accompanying with SADEN_UR6 will determine the given address
and broadcast address in 9-bit mode. The UART will response to both given
and broadcast address.
Follow the description to determine the given address and broadcast address:
21. given address: If bit n of SADEN_UR6 is “0”, then the corresponding bit of
SADDR_UR6 is don’t care.
22. broadcast address: If bit n of ORed SADDR_UR6 and SADEN_UR6 is “0”,
7-0
SADDR_UR6 R/W 00h
don’t care that bit. The remaining bit which is “1” is compared to the
received address.
Ex.
SADDR_UR6
0101_1100b
SADEN_UR6
1111_1001b
Given Address
0101_1xx0b
Broadcast Address
1111_11x1b
9bit-mode Slave Address Mask Register ⎯ Index F5h
Bit
Name
R/W Default
Description
This byte accompanying with SADDR_UR6 will determine the given address
and broadcast address in 9-bit mode. The UART_UR6 will response to both
given and broadcast address.
Follow the description to determine the given address and broadcast address:
23. given address: If bit n of SADEN_UR6 is “0”, then the corresponding bit of
SADDR_UR6 is don’t care.
24. broadcast address: If bit n of ORed SADDR_UR6 and SADEN_UR6 is “0”,
7:0
SADEN_UR6 R/W 00h
don’t care that bit. The remaining bit which is “1” is compared to the
received address.
Ex.
SADDR_UR6
0101_1100b
SADEN_UR6
1111_1001b
Given Address
0101_1xx0b
Broadcast Address
1111_11x1b
118
May, 2010
V0.28P
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