LCMXO1200E-3TN100CES 查看數據表（PDF） - Lattice Semiconductor
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LCMXO1200E-3TN100CES Datasheet PDF : 95 Pages
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Lattice Semiconductor
Architecture
MachXO Family Data Sheet
Bus Size Matching
All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB
word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for
each port varies, this mapping scheme applies to each port.
RAM Initialization and ROM Operation
If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block
during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a
ROM.
Memory Cascading
Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools
cascade memory transparently, based on specific design inputs.
Single, Dual, Pseudo-Dual Port and FIFO Modes
Figure 2-12 shows the five basic memory configurations and their input/output names. In all the sysMEM RAM
modes, the input data and address for the ports are registered at the input of the memory array. The output data of
the memory is optionally registered at the memory array output.
Figure 2-12. sysMEM Memory Primitives
AD[12:0]
DI[35:0]
CLK
CE
RST
WE
CS[2:0]
EBR
ADA[12:0]
DIA[17:0]
CLKA
DO[35:0]
CEA
RSTA
WEA
CSA[2:0]
DOA[17:0]
EBR
ADB[12:0]
DIB[17:0]
CEB
CLKB
RSTB
WEB
CSB[2:0]
DOB[17:0]
Single Port RAM
True Dual Port RAM
AD[12:0]
CLK
CE
RST
CS[2:0]
EBR
ADW[12:0]
DI[35:0]
CLKW
DO[35:0] CEW
WE
RST
CS[2:0]
EBR
ADR[12:0]
DO[35:0]
CER
CLKR
ROM
Pseudo-Dual Port RAM
DI[35:0]
CLKW
RSTA
WE
CEW
EBR
FIFO
DO[35:0]
CLKR
RSTB
RE
RCE
FF
AF
EF
AE
2-11
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