LCMXO1200E-3TN100CES 查看數據表（PDF） - Lattice Semiconductor

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LCMXO1200E-3TN100CES

MachXO Family Data Sheet

Lattice Semiconductor 

Lattice Semiconductor

Architecture

MachXO Family Data Sheet

output data signals are multiplexed and provide a single signal to the I/O pin via the sysIO buffer. Figure 2-17

shows the MachXO PIO logic.

The tristate control signal is multiplexed from the output data signals and their complements. In addition a global

signal (TSALL) from a dedicated pad can be used to tristate the sysIO buffer.

The PIO receives an input signal from the pin via the sysIO buffer and provides this signal to the core of the device.

In addition there are programmable elements that can be utilized by the design tools to avoid positive hold times.

Figure 2-17. MachXO PIO Block Diagram

From Routing

From Routing

Fast Output

Data signal

TS

TSALL

sysIO

Buffer

DO

TO

PAD

1

Input

Data Signal

2

3

Programmable

Delay Elements

+

4-

Note: Buffer 1 tracks with VCCAUX

Buffer 2 tracks with VCCIO.

Buffer 3 tracks with internal 1.2V VREF.

Buffer 4 is available in MachXO1200 and MachXO2280 devices only.

From Complementary

Pad

sysIO Buffer

Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the

periphery of the device in groups referred to as Banks. The sysIO buffers allow users to implement the wide variety

of standards that are found in today’s systems including LVCMOS, TTL, BLVDS, LVDS and LVPECL.

In the MachXO devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS and PCI) are pow-

ered using VCCIO. In addition to the Bank VCCIO supplies, the MachXO devices have a VCC core logic power supply,

and a VCCAUX supply that powers up a variety of internal circuits including all the differential and referenced input buff-

ers.

MachXO256 and MachXO640 devices contain single-ended input buffers and single-ended output buffers with

complementary outputs on all the I/O Banks.

MachXO1200 and MachXO2280 devices contain two types of sysIO buffer pairs.

1. Top and Bottom sysIO Buffer Pairs

The sysIO buffer pairs in the top and bottom Banks of the device consist of two single-ended output drivers and

two sets of single-ended input buffers (for ratioed or absolute input levels). The I/O pairs on the top and bottom

2-15

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