LCMXO1200E-3TN100CES 查看數據表（PDF） - Lattice Semiconductor

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LCMXO1200E-3TN100CES

MachXO Family Data Sheet

Lattice Semiconductor 

Lattice Semiconductor

Architecture

MachXO Family Data Sheet

The EBR memory supports three forms of write behavior for single or dual port operation:

1. Normal – data on the output appears only during the read cycle. During a write cycle, the data (at the current

address) does not appear on the output. This mode is supported for all data widths.

2. Write Through – a copy of the input data appears at the output of the same port. This mode is supported for all

data widths.

3. Read-Before-Write – when new data is being written, the old contents of the address appears at the output.

This mode is supported for x9, x18 and x36 data widths.

FIFO Configuration

The FIFO has a write port with Data-in, CEW, WE and CLKW signals. There is a separate read port with Data-out,

RCE, RE and CLKR signals. The FIFO internally generates Almost Full, Full, Almost Empty and Empty Flags. The

Full and Almost Full flags are registered with CLKW. The Empty and Almost Empty flags are registered with CLKR.

The range of programming values for these flags are in Table 2-7.

Table 2-7. Programmable FIFO Flag Ranges

Flag Name

Full (FF)

Almost Full (AF)

Almost Empty (AE)

Empty (EF)

N = Address bit width

Programming Range

1 to (up to 2N-1)

1 to Full-1

1 to Full-1

0

The FIFO state machine supports two types of reset signals: RSTA and RSTB. The RSTA signal is a global reset

that clears the contents of the FIFO by resetting the read/write pointer and puts the FIFO flags in their initial reset

state. The RSTB signal is used to reset the read pointer. The purpose of this reset is to retransmit the data that is in

the FIFO. In these applications it is important to keep careful track of when a packet is written into or read from the

FIFO.

Memory Core Reset

The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-

nously. RSTA and RSTB are local signals, which reset the output latches associated with Port A and Port B respec-

tively. The Global Reset (GSRN) signal resets both ports. The output data latches and associated resets for both

ports are as shown in Figure 2-13.

2-12

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