LCMXO1200E-3TN100CES 查看數據表（PDF） - Lattice Semiconductor

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LCMXO1200E-3TN100CES

MachXO Family Data Sheet

Lattice Semiconductor 

Lattice Semiconductor

Architecture

MachXO Family Data Sheet

PIO Groups

On the MachXO devices, PIO cells are assembled into two different types of PIO groups, those with four PIO cells

and those with six PIO cells. PIO groups with four IOs are placed on the left and right sides of the device while PIO

groups with six IOs are placed on the top and bottom. The individual PIO cells are connected to their respective

sysIO buffers and PADs.

On all MachXO devices, two adjacent PIOs can be joined to provide a complementary Output driver pair. The I/O

pin pairs are labeled as "T" and "C" to distinguish between the true and complement pins.

The MachXO1200 and MachXO2280 devices contain enhanced I/O capability. All PIO pairs on these larger

devices can implement differential receivers. In addition, half of the PIO pairs on the left and right sides of these

devices can be configured as LVDS transmit/receive pairs. PIOs on the top of these larger devices also provide PCI

support.

Figure 2-15. Group of Four Programmable I/O Cells

This structure is used on the

left and right of MachXO devices

PIO A

PADA "T"

Four PIOs

PIO B

PIO C

PADB "C"

PADC "T"

PIO D

PADD "C"

Figure 2-16. Group of Six Programmable I/O Cells

This structure is used on the top

and bottom of MachXO devices

PIO A

PADA "T"

Six PIOs

PIO B

PIO C

PIO D

PADB "C"

PADC "T"

PADD "C"

PIO E

PADE "T"

PIO F

PADF "C"

PIO

The PIO blocks provide the interface between the sysIO buffers and the internal PFU array blocks. These blocks

receive output data from the PFU array and a fast output data signal from adjacent PFUs. The output data and fast

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