TA16S1FAA 查看數據表（PDF） - Agere -> LSI Corporation

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TA16S1FAA

TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Agere -> LSI Corporation 

Data Sheet

March 2001

TA16-Type 2.5 Gbits/s Transponder with

16-Channel 155 Mbits/s Multiplexer/Demulitplexer

Functional Description (continued)

Loopback Modes

The TA16 transponder is capable of operating in either

of two loopback modes: diagnostic loopback or line

loopback.

Line Loopback

When LLOOP is pulled low, the received serial data

stream and recovered 2488.32 MHz serial clock from

the optical receiver are connected directly to the serial

data and clock inputs of the optical transmitter. This

establishes a receive-to-transmit loopback at the serial

line rate.

Diagnostic Loopback

When DLOOP is pulled low, a loopback path is estab-

lished from the transmitter to the receiver. In this mode,

the serial data from the parallel-to-serial converter and

the transmit serial clock are looped back to the serial-

to-parallel converter and the frame and byte detect cir-

cuitry, respectively.

Transponder Interfacing

The TxD[0:15]P/N and PICLKP/N inputs and the

RxQ[0:15]P/N, POCLKP/N, and PCLKP/N outputs are

high-speed (155 Mbits/s), LVPECL differential data and

clock signals. To maintain optimum signal fidelity, these

inputs and outputs must be connected to their termi-

nating devices via 50 Ω controlled-impedance trans-

mission lines. The transmitter inputs (TxD[0:15]P/N,

TxREFCLKP/N, and PICLKP/N) must be terminated as

close as possible to theTA16 transponder connector

with a Thevenin equivalent impedance equal to 50 ¾

terminated to Vcc – 2V. The receiver outputs

(RxQ[0:15]P/N, POCLKP/N, and PCLKP/N) must be ter-

minated as close as possible to the device (IC) that

these signals interface to with a Thevenin equivalent

impedance equal to 50 Ω terminated to Vcc – 2 V.

Figure 3, below, shows one example of the proper ter-

minations. Other methods may be used, provided they

meet the requirements stated above.

TxREFCLKP/N. The reference clock input is different

than the TxD and PICLK inputs because it is internally

terminated, ac-coupled, and self-biased. Therefore, it

must be treated somewhat differently than the TxD and

PICLK inputs. Figure 14 shows the proper method for

connecting the TxREFCLK input.

SONET/SDH

INTERFACE IC

TxLINE

3.3 V

130 Ω

50 Ω IMPEDANCE

TRANSMISSION LINES

3.3 V

80 Ω

130 Ω

80 Ω

TA16-TYPE TRANSPONDER

TxD[0:15]P

(LVPECL)

MUX

Tx

TxD[0:15]N

(LVPECL)

RxLINE

130 Ω

80 Ω

130 Ω

50 Ω IMPEDANCE

TRANSMISSION LINES

80 Ω

RxD[0:15]P

(LVPECL)

DEMUX

Rx

RxD[0:15]N

(LVPECL)

Agere Systems Inc.

Figure 3. Transponder Interfacing

1-1054(F)

13

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