TA16S1FAA 查看數據表（PDF） - Agere -> LSI Corporation

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TA16S1FAA

TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Agere -> LSI Corporation 

TA16-Type 2.5 Gbits/s Transponder with

16-Channel 155 Mbits/s Multiplexer/Demulitplexer

Data Sheet

March 2001

Timing Characteristics (continued)

Forward Clocking

In some applications, it is necessary to forward-clock

the data in a SONET/SDH system. In this application,

the reference clock from which the high-speed serial

clock is synthesized and the parallel data clock both

originate from the same source on the customer appli-

cation circuit. The timing control logic in theTA16 tran-

sponder transmitter automatically generates an internal

load signal that has a fixed relationship to the reference

clock. The logic takes into account the variation of the

reference clock to the internal load signal over temper-

ature and voltage. The connections required to imple-

ment this clocking method are shown in Figure 6. The

setup and hold times for PICLK to TxD[0:15] must be

met by the customer logic.

Possible problems: to meet the jitter generation specifi-

cations required by SONET/SDH, the jitter of the refer-

ence clock must be minimized. It could be difficult to

meet the SONET jitter generation specifications using

a reference clock generated from the customer logic.

OSCILLATOR

155.52 MHz ± 20 ppm

CLOCK

BUFFER

TXREFCLK

CLOCK

DATA

PCLK

TXREFCLK

DIVIDER

PLL

PICLK

INTERNAL

PCLK

16

TXD[0:15]

TIMING

GENERATOR

FIFO

PHERR

PHINIT

CENTERS

FIFO

CUSTOMER LOGIC

LOCKDET

TA16 TRANSPONDER

Figure 6. Forward Clocking of theTA16 Transmitter

1-1122(F)

200

Agere Systems Inc.

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