TA16S1FAA 查看數據表（PDF） - Agere -> LSI Corporation

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TA16S1FAA

TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Agere -> LSI Corporation 

Data Sheet

March 2001

TA16-Type 2.5 Gbits/s Transponder with

16-Channel 155 Mbits/s Multiplexer/Demulitplexer

Timing Characteristics

Transmitter Data Input Timing

The TA16 transponder utilizes a unique FIFO to decou-

ple the internal and external (PICLK) clocks. The FIFO

can be initialized, which allows the system designer to

have an infinite PCLK-to-PICLK delay through this inter-

facing logic (ASIC or commercial chip set). The config-

uration of the FIFO is dependent upon the I/O pins,

which comprise the synch timing loop. This loop is

formed from PHERR to PHINIT and PCLK to PICLK.

The FIFO can be thought of as a memory stack that

can be initialized by PHINT or LOCKDET. The PHERR

signal is a pointer that goes high when a potential tim-

ing mismatch is detected between PICLK and the inter-

nally generated PCLK clock. When PHERR is fed back

to PHINIT, it initializes the FIFO so that it does not over-

flow or underflow.

The internally generated divide-by-16 clock is used to

clock out data from the FIFO. PHINIT and LOCKDET

signals will center the FIFO after the third PICLK pulse.

This is done to ensure that PICLK is stable. This

scheme allows the user to have an infinite PCLK to

PICLK delay through the ASIC. Once the FIFO is cen-

tered, the PCLK and PICLK can have a maximum drift of

±5 ns.

During normal operation, the incoming data is passed

from the PICLK input timing domain to the internally

generated divide-by-16 PCLK timing domain. Although

the frequency of PICLK and PCLK are the same, their

phase relationship is arbitrary. To prevent errors

caused by short setup or hold times between the two

domains, the timing generator circuitry monitors the

phase relationship between PICLK and PCLK.

When an FIFO timing violation is detected, the phase

error (PHERR) signal pulses high. If the condition per-

sists, PHERR will remain high. When PHERR is fed

back into the PHINIT input (by shorting them on the

printed-circuit board [PCB]), PHINIT will initialize the

FIFO if PHINIT is held high for at least two byte clocks.

The initialization of the FIFO prevents PCLK and PICLK

from concurrently trying to read and write over the

same FIFO bank.

During realignment, one to three bytes (16-bits wide)

will be lost. Alternatively, the customer logic can take in

the PHERR signal, process it, and send an output to

the PHINIT input in such a way that only idle bytes are

lost during the initialization of the FIFO. Once the FIFO

has been initialized, PHERR will go inactive.

Agere Systems Inc.

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