MCP23016 查看數據表（PDF） - Microchip Technology

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MCP23016

16-Bit I2C™ I/O Expander

Microchip Technology 

MCP23016

TABLE 2-5: I2C BUS DATA REQUIREMENTS

Param

No.

Symbol

Characteristic

Min

Max Units

Conditions

100

101

102

103

90

91

106

107

92

109

110

111

Note 1:

2:

3:

THIGH Clock High Time 100 kHz mode

4.0

—

µs (Note 1)

400 kHz mode

0.6

—

µs

TLOW Clock Low Time 100 kHz mode

4.7

—

µs (Note 1)

400 kHz mode

1.3

—

µs

TR SDA and SCL Rise 100 kHz mode

—

1000 ns (Note 1)

Time

400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from

10 - 400 pF

TF SDA and SCL Fall 100 kHz mode

—

300 ns (Note 1)

Time

400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from

10 - 400 pF

TSU:STA START Condition 100 kHz mode

4.7

Setup Time

400 kHz mode

0.6

—

µs Only relevant for repeated

—

µs START condition (Note 1)

THD:STA START Condition 100 kHz mode

4.0

Hold Time

400 kHz mode

0.6

—

µs After this period, the first

—

µs clock pulse is generated

(Note 1)

THD:DAT Data Input Hold 100 kHz mode

0

Time

400 kHz mode

0

—

ns (Note 1)

0.9 µs

TSU:DAT Data Input Setup 100 kHz mode

250

Time

400 kHz mode

100

—

ns (Note 1) (Note 3)

—

ns

TSU:STO STOP Condition 100 kHz mode

4.7

Setup Time

400 kHz mode

0.6

—

µs (Note 1)

—

µs

TAA Output Valid from 100 kHz mode

—

3500 ns (Note 1) (Note 2)

Clock

400 kHz mode

—

—

ns

TBUF Bus Free Time

100 kHz mode

4.7

400 kHz mode

1.3

—

µs Time the bus must be free

—

µs before a new transmis-

sion can start (Note 1)

CB Bus Capacitive Loading

—

400 pF

TWAIT Clock wait time

after ninth pulse

100 kHz mode

400 kHz mode

12 µs

12 µs

—

µs Time the bus must remain

—

µs free after the ninth clock

pulse before a new

transmission can start.

These parameters are characterized but not tested.

As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the

requirement TSU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not

stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,

it must output the next data bit to the SDA line TR max.+TSU:DAT = 1000 + 250 = 1250 ns (according to the

Standard mode I2C bus specification), before the SCL line is released.

DS20090C-page 24

© 2007 Microchip Technology Inc.

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