CMX644A 查看數據表（PDF） - CML Microsystems Plc

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CMX644A

V.22 and Bell 212A Modem

CML Microsystems Plc 

V22 and Bell 212A Modem

LOOPBACK L1 and L0

(Bits 3 and 2)

XTAL FRQ X1 and X0

(Bits 1 and 0)

CMX644A

These 2 bits control internal signal paths such that loopback tests can

be performed. Function is according to the following table:

L1

Bit 3

0

0

1

1

L0

Bit 2

0

1

0

1

Normal Device Operation: no loopback.

Local Analogue Loopback: the output of the Tx

gain block is routed to the input of the receiver

gain block. (The connection between the receiver

op-amp and gain block is broken).

Local Digital Loopback: data is loaded into the

TX DATA BYTE register in the usual way via the

‘C-BUS’ when indicated by the TX DATA READY

flag. This digital data is internally retimed serially

to the modem bit-rate and is then clocked into the

receiver buffer. When the receiver buffer is full

the RX DATA READY flag will be set and the data

can then be read out of RX DATA BYTE register

via the ‘C-BUS’.

Reserved for future use.

These two bits control the internal primary clock dividers to allow for a

choice of 3 crystal frequencies. They can also be set to put the device

into ‘Zero Power’ mode: in this mode all functions are powersaved,

except for the ‘C-BUS’ and the Ring Detector. In ‘Zero Power’ the

crystal oscillator is disabled and the Bias resistor chain is disconnected

from the supplies.

Note: When the device is brought out of ‘Zero Power’ mode, the

software should allow at least 20ms for the crystal oscillator to re-start

and for the Bias capacitor to re-charge, before proceeding with any

further device functions. The function is given by the following table:

X1

Bit 1

0

0

1

1

X0

Bit 0

0

1

0

1

Crystal / Mode

‘Zero Power’

3.6864MHz crystal

7.3728MHz crystal

11.0592MHz crystal

© 2000 Consumer Microcircuits Limited

11

D/644A/6

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