1EDF5673KXUMA1 查看數據表（PDF） - Infineon Technologies

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1EDF5673KXUMA1

GaN EiceDRIVER™ product family

Infineon Technologies 

GaN EiceDRIVER™ product family

GaN gate driver

Functional description

100 mW. It should also be pointed out that the internal gate/source clamp implemented in CoolGaN™ is

connected in parallel with Rss in this state. To avoid any significant additional current and power dissipation, VDDO

should be strictly limited to a maximum of 12 V.

As a summary, the total gate-drive power always stays in the 50 to 150 mW range and is thus sufficiently small to

not cause any critical on-chip temperature increase.

3.4

Driver outputs

The rail-to-rail driver output stage realized with complementary MOS transistors is able to provide a typical 4 A

sourcing and 8 A sinking current. Although these current levels are neither needed nor reached when driving

GaN HEMTs (due to their low gate charge of only a few nC), the low on-resistance coming together with high

driving current is nevertheless beneficial. With an Ron of 0.85 Ω for the sourcing pMOS and 0.35 Ω for the sinking

nMOS transistor the driver can be considered as a nearly ideal switch. The gate drive parameters can thus be

determined easily and accurately by the external components as described in Chapter 2. The p-channel sourcing

transistor enables real rail-to-rail behavior without suffering from the voltage drop unavoidably associated with

nMOS source follower stages.

3.5

Undervoltage Lockout (UVLO)

The Undervoltage Lockout function ensures that the outputs can be switched only, if both input and output

supply voltages exceed the corresponding UVLO threshold voltages. Thus it can be guaranteed, that the switch

transistors are not operated, if the driving voltage is too low for complete and fast switching on, thereby avoiding

excessive power dissipation.

The UVLO levels for the output supply are set to a typical "on" value of 4.5 and 5.5 V (with 0.3 V hysteresis) for

OUTG and OUTS, respectively, whereas UVLOin for VDDI is set to 2.85 V with 0.15 V hysteresis. The different UVLO

levels for OUTG and OUTS help to safely avoid any erroneous turn-on of the GaN switch despite the low GaN

threshold voltage. Special attention has been paid to cover all possible operating conditions, like start-up or

arbitrary supply voltage situations:

• if VDDI drops below UVLOin, a "switch-to-low" command is sent to output OUTG, whereas OUTS is switched to

"high"; this corresponds to the final state in extended "off" periods with VGS = -VDDO

• for VDD lower than the output UVLO levels, an effective clamping concept has been realized by means of 100 kΩ

resistors connecting the outputs OUTS and OUTG to the respective gates of the sourcing pMOS transistors in

the output stage

As a result, safe operation of the GaN switch can be guaranteed under any circumstances.

3.6

CT communication and data transmission

A coreless transformer (CT) based communication module is used for PWM signal transfer between input and

outputs. A proven high-resolution pulse repetition scheme in the transmitter combined with a watchdog time-

out at the receiver side enables recovery from communication fails and ensures safe system shut-down in failure

cases.

Besides, the repetition scheme is also used to signal a "first pulse" situation (Figure 5). If an "off"-state lasts

longer than 32 µs, the repetition rate of the CT pulses is reduced to a value that causes the watchdog on the

output chip to wake up and initiate a change in the "off" state acc. to Figure 5 (switch S3 to "off" and S4 to "on"

state).

3.7

Signal timing

From the above, the extended "off"-phase t2 defining a "first pulse" situation, is fixed at a typical value of 32 µs.

The other important timing parameter t1, i.e. the duration of the negative "off"-voltage, can be programmed by

Final datasheet

11

Rev. 2.3

2020-10-22

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