VSC6511 查看數據表（PDF） - Vitesse Semiconductor
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VSC6511 Datasheet PDF : 22 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC6511
SMPTE 292M Serializer, Deserialzer, and
Deserializer/Reclocker
The following functional blocks are used in the Deserializer mode of operation. Please refer to the Functional
Description at the beginning of this document for the a description of each of these blocks.
Clock Multiplier Unit (CMU)
Serial Input
Clock Recovery Unit
Deserializer
Descrambler and NRZI Decoder
CRC Checker
Frame Aligner and SAV/EAV Output
Figure 9: Receive Timing Waveforms (Deserializer Mode)
RCLK
D[19:0]
t1
t2
Data Valid
Table 3: Receive AC Characteristics (Deserializer Mode)
Symbol
Parameter
Min Typ Max
t1
TTL Outputs valid prior to RCLK rise 3.0
t2
TTL Outputs valid after RCLK rise
2.0
tR, tF
TTL Output rise and fall time
2.0
tLOCK
Data acquisition lock time at 1.485Gb/s
10
Note: The RCLK output from the CRU is 40% high and 60% low by design.
Unit
ns
ns
ns
us
Condition
See Figure 9. Not 100% tested.
See Figure 9. Not 100% tested.
Between VIL(MAX) and
VIH(MIN), into 10pF load. Not
100% tested.
For clean, error free PRBS data.
Not 100% tested.
G52311-0, Rev 2.1
6/25/01
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