ISL8204M 查看數據表（PDF） - Renesas Electronics

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ISL8204M

Complete High Efficiency DC/DC Power Module

Renesas Electronics 

ISL8204M, ISL8206M

overcurrent retries. If the output is shorted to GND during

soft-start, the OCP will handle it, as described in the next section.

Overcurrent Protection (OCP)

The overcurrent function protects the converter from a shorted

output by using the low-side MOSFET ON-resistance, rDS(ON), to

monitor the current. A resistor (RSET) programs the overcurrent

trip level.

This method enhances the converter's efficiency and reduces

cost by eliminating a current sensing resistor. If overcurrent is

detected, the output immediately shuts off. It cycles the soft-start

function in a hiccup mode (2 dummy soft-start time-outs, then up

to one real one) to provide fault protection. If the shorted

condition is not removed, this cycle will continue indefinitely.

Following POR (and 6.8ms delay), the ISL8204M, ISL8206M

initiates the overcurrent protection sample and hold operation.

The low-side gate driver is disabled to allow an internal 21.5µA

current source to develop a voltage across RSET. The ISL8204M,

ISL8206M samples this voltage (which is referenced to the PGND

pin) at the ISET pin, and holds it in a counter and DAC

combination. This sampled voltage is held internally as the

overcurrent set point, for as long as power is applied, or until a

new sample is taken after coming out of a shutdown.

The actual monitoring of the low-side MOSFET ON-resistance

starts 200ns (nominal) after the edge of the internal PWM logic

signal (that creates the rising external low-side gate signal). This

is done to allow the gate transition noise and ringing on the

PHASE pin to settle out before monitoring. The monitoring ends

when the internal PWM edge (and thus low-side gate signal) goes

low. The OCP can be detected anywhere within the above

window.

If the converter is running at high duty cycles, around 75% for

600kHz operation, then the low-side gate pulse width may not be

wide enough for the OCP to properly sample the rDS(ON). For those

cases, if the low-side gate signal is too narrow (or not there at all)

for 3 consecutive pulses, then the third pulse will be stretched

and/or inserted to the 425ns minimum width. This allows for

OCP monitoring every third pulse under this condition. This can

introduce a small pulse-width error on the output voltage, which

will be corrected on the next pulse; and the output ripple voltage

will have an unusual 3-clock pattern, which may look like jitter.

The overcurrent function will trip at a peak inductor current

(IPEAK) determined by Equation 2:

IPEAK = 2----------I-r-S--D--E--S--T----O----N-R-----S----E----T-

(EQ. 2)

where:

ISET is the internal ISET current source (21.5µA typical).

RSET is equivalent resistance between ISET and PGND pins.

rDS(ON) is typically 15m at (VPVCC = VGS = 10V, IDS = 15A) and

18m at (VPVCC = VGS = 4.5V, IDS = 15A).

Note: ISL8204M, ISL8206M has integrated 4.12k2.87k

resistance (RSET-IN). Therefore, the equivalent resistance of RSET

can be expressed in Equation 3:

RSET = -RR----SS----EE----TT--------EE----XX-----+----RR-----SS----EE----TT--------II-NN---

(EQ. 3)

The scale factor of 2 doubles the trip point of the MOSFET voltage

drop, compared to the setting on the RSET resistor. The OC trip

point varies in a system mainly due to the MOSFET rDS(ON)

variations (i.e. over process, current and temperature). To avoid

overcurrent tripping in the normal operating load range, find the

RSET resistor from Equation 3, and use the following values:

1. The maximum rDS(ON) at the highest junction temperature

2. The minimum ISET from the “Electrical Specifications” table

on page 3.

3. Determine IPEAK for:

IPEAK  IOUTMAX + ------2-I--L----

(EQ. 4)

where IL is the output inductor ripple current. In a high input

voltage, high output voltage application, such as 20V input to 5V

output, the inductor ripple becomes excessive due to the fix

internal inductor value. In such applications, the output current will

be limited from the rating to approximately 70% of the module’s

rated current.

The relationships between the external RSET values and the

typical output current IOUT(MAX) OCP levels for ISL8206M are as

follows:

RSET

()

OPEN

50k

20k

10k

5k

TABLE 3.

OCP (A) at

VIN = 12V,

PVCC = 5V

8.1

7.5

6.6

5.5

4.4

OCP (A) at

VIN = 12V

PVCC = 12V

8.8

8.1

7.4

6.4

5.0

The range of allowable voltages detected (2 x ISET x RSET) is 0mV to

475mV. If the voltage drop across RSET is set too low, the following

conditions may occur: (1) Continuous OCP tripping and retry and

(2) It may be overly sensitive to system noise and in-rush current

spikes, so it should be avoided. The maximum usable setting is

around 0.2V across RSET (0.4V across the MOSFET); values above

this might disable the protection. Any voltage drop across RSET

that is greater than 0.3V (0.6V MOSFET trip point) will disable the

OCP. Note that conditions during power-up or during a retry may

look different than normal operation. During power-up in a 12V

system, the ISL8204M, ISL8206M starts operation just above 4V;

if the supply ramp is slow, the soft-start ramp might be over well

before 12V is reached. Therefore, with low-side gate drive voltages,

the rDS(ON) of the MOSFET will be higher during power-up,

effectively lowering the OCP trip. In addition, the ripple current will

likely be different at a lower input voltage. Another factor is the

digital nature of the soft-start ramp. On each discrete voltage step,

there is in effect, a small load transient and a current spike to

charge the output capacitors. The height of the current spike is not

FN6999 Rev 4.00

October 28, 2014

Page 12 of 19

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